mirror of https://gitee.com/openkylin/linux.git
oprofile/x86: move IBS code
Moving code to make future changes easier. This groups all IBS code together. Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
parent
8617f98c00
commit
da759fe5be
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@ -102,116 +102,6 @@ static u32 get_ibs_caps(void)
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return ibs_caps;
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#endif
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/* functions for op_amd_spec */
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!msrs->counters[i].addr)
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continue;
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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}
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static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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goto fail;
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if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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goto fail;
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}
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/* both registers must be reserved */
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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op_amd_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* setup reset_value */
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for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
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if (counter_config[i].enabled
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&& msrs->counters[op_x86_virt_to_phys(i)].addr)
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reset_value[i] = counter_config[i].count;
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else
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reset_value[i] = 0;
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}
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/* clear all counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!msrs->controls[i].addr)
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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/*
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* avoid a false detection of ctr overflows in NMI
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* handler
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*/
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wrmsrl(msrs->counters[i].addr, -1LL);
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}
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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/*
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* 16-bit Linear Feedback Shift Register (LFSR)
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*
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@ -376,6 +266,116 @@ static void op_amd_stop_ibs(void)
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wrmsrl(MSR_AMD64_IBSOPCTL, 0);
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#endif
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/* functions for op_amd_spec */
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!msrs->counters[i].addr)
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continue;
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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}
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static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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goto fail;
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if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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goto fail;
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}
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/* both registers must be reserved */
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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op_amd_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* setup reset_value */
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for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
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if (counter_config[i].enabled
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&& msrs->counters[op_x86_virt_to_phys(i)].addr)
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reset_value[i] = counter_config[i].count;
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else
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reset_value[i] = 0;
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}
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/* clear all counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!msrs->controls[i].addr)
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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/*
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* avoid a false detection of ctr overflows in NMI
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* handler
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*/
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wrmsrl(msrs->counters[i].addr, -1LL);
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}
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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