mirror of https://gitee.com/openkylin/linux.git
clk: tegra: Rename sor0_lvds to sor0_out
This makes Tegra124 and Tegra210 consistent with subsequent Tegra generations. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -236,7 +236,7 @@ enum clk_id {
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tegra_clk_soc_therm,
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tegra_clk_soc_therm,
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tegra_clk_soc_therm_8,
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tegra_clk_soc_therm_8,
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tegra_clk_sor0,
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tegra_clk_sor0,
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tegra_clk_sor0_lvds,
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tegra_clk_sor0_out,
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tegra_clk_sor1,
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tegra_clk_sor1,
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tegra_clk_sor1_out,
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tegra_clk_sor1_out,
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tegra_clk_spdif,
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tegra_clk_spdif,
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@ -847,7 +847,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
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[tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
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[tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
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[tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
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[tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
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[tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
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[tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
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[tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
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[tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },
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[tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
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[tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
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[tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
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[tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
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[tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
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[tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
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@ -1011,14 +1011,14 @@ static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
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};
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};
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#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
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#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
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static const char *mux_clkm_plldp_sor0lvds[] = {
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static const char *mux_clkm_plldp_sor0out[] = {
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"clk_m", "pll_dp", "sor0_lvds",
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"clk_m", "pll_dp", "sor0_out",
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};
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};
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#define mux_clkm_plldp_sor0lvds_idx NULL
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#define mux_clkm_plldp_sor0out_idx NULL
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static struct tegra_periph_init_data tegra124_periph[] = {
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static struct tegra_periph_init_data tegra124_periph[] = {
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MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
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MUX8_NOGATE_LOCK("sor0_out", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_out, &sor0_lock),
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NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
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NODIV("sor0", mux_clkm_plldp_sor0out, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
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};
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};
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static struct clk **clks;
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static struct clk **clks;
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@ -2351,7 +2351,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
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[tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
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[tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
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[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
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[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
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[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
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[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
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[tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
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[tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },
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[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
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[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
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[tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },
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[tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },
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[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
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[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
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