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net: phy: dp83867: perform soft reset and retain established link
Current logic is performing hard reset and causing the programmed registers to be wiped out. as per datasheet: https://www.ti.com/lit/ds/symlink/dp83867cr.pdf 8.6.26 Control Register (CTRL) do SW_RESTART to perform a reset not including the registers, If performed when link is already present, it will drop the link and trigger re-auto negotiation. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Geet Modi <geet.modi@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -826,16 +826,12 @@ static int dp83867_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
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err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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/* After reset FORCE_LINK_GOOD bit is set. Although the
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* default value should be unset. Disable FORCE_LINK_GOOD
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* for the phy to work properly.
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*/
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return phy_modify(phydev, MII_DP83867_PHYCTRL,
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DP83867_PHYCR_FORCE_LINK_GOOD, 0);
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}
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