From daaff6e95b435ae691e6004b5dcfb13c71c1cd45 Mon Sep 17 00:00:00 2001 From: Jingchang Lu Date: Fri, 8 Nov 2013 18:01:53 +0800 Subject: [PATCH] ARM: imx: Add DMAMUX clock for Vybrid vf610 SoC Signed-off-by: Jingchang Lu Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-vf610.c | 5 +++++ include/dt-bindings/clock/vf610-clock.h | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index b169a396d93b..ecd66d8e20b6 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); + clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); + clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); + clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 4aa2b48cd151..a91602951d3d 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -160,6 +160,10 @@ #define VF610_CLK_GPU2D 147 #define VF610_CLK_ENET0 148 #define VF610_CLK_ENET1 149 -#define VF610_CLK_END 150 +#define VF610_CLK_DMAMUX0 150 +#define VF610_CLK_DMAMUX1 151 +#define VF610_CLK_DMAMUX2 152 +#define VF610_CLK_DMAMUX3 153 +#define VF610_CLK_END 154 #endif /* __DT_BINDINGS_CLOCK_VF610_H */