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clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
Product datasheet recommends different values for UPLL and PLLA analog control register. Adapt accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1573478913-19737-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -25,7 +25,8 @@
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#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
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#define PMC_PLL_ACR 0x18
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#define PMC_PLL_ACR_DEFAULT 0x1b040010UL
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#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL
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#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL
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#define PMC_PLL_ACR_UTMIVR BIT(12)
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#define PMC_PLL_ACR_UTMIBG BIT(13)
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#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
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@ -88,7 +89,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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}
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/* Recommended value for PMC_PLL_ACR */
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val = PMC_PLL_ACR_DEFAULT;
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if (pll->characteristics->upll)
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val = PMC_PLL_ACR_DEFAULT_UPLL;
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else
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val = PMC_PLL_ACR_DEFAULT_PLLA;
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regmap_write(regmap, PMC_PLL_ACR, val);
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regmap_write(regmap, PMC_PLL_CTRL1,
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