mirror of https://gitee.com/openkylin/linux.git
gianfar: remove gianfar_mii.c
commit 1577ecef76
Author: Andy Fleming <afleming@freescale.com>
Date: Wed Feb 4 16:42:12 2009 -0800
netdev: Merge UCC and gianfar MDIO bus drivers
left out the deletion of gianfar_mii.c.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Andy Fleming
David S. Miller
parent
bda6a15a0d
commit
db46db1577
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@ -1,379 +0,0 @@
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/*
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* drivers/net/gianfar_mii.c
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*
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* Gianfar Ethernet Driver -- MIIM bus implementation
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* Provides Bus interface for MIIM regs
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala
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*
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* Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include "gianfar.h"
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#include "gianfar_mii.h"
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/*
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* Write value to the PHY at mii_id at register regnum,
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* on the bus attached to the local interface, which may be different from the
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* generic mdio bus (tied to a single interface), waiting until the write is
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* done before returning. This is helpful in programming interfaces like
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* the TBI which control interfaces like onchip SERDES and are always tied to
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* the local mdio pins, which may not be the same as system mdio bus, used for
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* controlling the external PHYs, for example.
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*/
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int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
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int regnum, u16 value)
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{
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/* Set the PHY address and the register address we want to write */
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gfar_write(®s->miimadd, (mii_id << 8) | regnum);
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/* Write out the value we want */
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gfar_write(®s->miimcon, value);
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/* Wait for the transaction to finish */
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while (gfar_read(®s->miimind) & MIIMIND_BUSY)
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cpu_relax();
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return 0;
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}
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/*
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* Read the bus for PHY at addr mii_id, register regnum, and
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* return the value. Clears miimcom first. All PHY operation
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* done on the bus attached to the local interface,
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* which may be different from the generic mdio bus
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* This is helpful in programming interfaces like
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* the TBI which, inturn, control interfaces like onchip SERDES
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* and are always tied to the local mdio pins, which may not be the
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* same as system mdio bus, used for controlling the external PHYs, for eg.
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*/
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int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum)
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{
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u16 value;
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/* Set the PHY address and the register address we want to read */
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gfar_write(®s->miimadd, (mii_id << 8) | regnum);
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/* Clear miimcom, and then initiate a read */
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gfar_write(®s->miimcom, 0);
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gfar_write(®s->miimcom, MII_READ_COMMAND);
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/* Wait for the transaction to finish */
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while (gfar_read(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
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cpu_relax();
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/* Grab the value of the register from miimstat */
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value = gfar_read(®s->miimstat);
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return value;
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}
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/* Write value to the PHY at mii_id at register regnum,
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* on the bus, waiting until the write is done before returning.
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* All PHY configuration is done through the TSEC1 MIIM regs */
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int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
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{
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struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv;
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/* Write to the local MII regs */
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return(gfar_local_mdio_write(regs, mii_id, regnum, value));
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}
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/* Read the bus for PHY at addr mii_id, register regnum, and
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* return the value. Clears miimcom first. All PHY
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* configuration has to be done through the TSEC1 MIIM regs */
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int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv;
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/* Read the local MII regs */
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return(gfar_local_mdio_read(regs, mii_id, regnum));
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}
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/* Reset the MIIM registers, and wait for the bus to free */
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static int gfar_mdio_reset(struct mii_bus *bus)
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{
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struct gfar_mii __iomem *regs = (void __force __iomem *)bus->priv;
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unsigned int timeout = PHY_INIT_TIMEOUT;
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mutex_lock(&bus->mdio_lock);
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/* Reset the management interface */
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gfar_write(®s->miimcfg, MIIMCFG_RESET);
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/* Setup the MII Mgmt clock speed */
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gfar_write(®s->miimcfg, MIIMCFG_INIT_VALUE);
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/* Wait until the bus is free */
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while ((gfar_read(®s->miimind) & MIIMIND_BUSY) &&
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--timeout)
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cpu_relax();
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mutex_unlock(&bus->mdio_lock);
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if(timeout == 0) {
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printk(KERN_ERR "%s: The MII Bus is stuck!\n",
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bus->name);
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return -EBUSY;
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}
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return 0;
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}
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/* Allocate an array which provides irq #s for each PHY on the given bus */
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static int *create_irq_map(struct device_node *np)
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{
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int *irqs;
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int i;
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struct device_node *child = NULL;
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irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
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if (!irqs)
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return NULL;
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for (i = 0; i < PHY_MAX_ADDR; i++)
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irqs[i] = PHY_POLL;
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while ((child = of_get_next_child(np, child)) != NULL) {
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int irq = irq_of_parse_and_map(child, 0);
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const u32 *id;
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if (irq == NO_IRQ)
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continue;
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id = of_get_property(child, "reg", NULL);
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if (!id)
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continue;
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if (*id < PHY_MAX_ADDR && *id >= 0)
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irqs[*id] = irq;
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else
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printk(KERN_WARNING "%s: "
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"%d is not a valid PHY address\n",
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np->full_name, *id);
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}
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return irqs;
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}
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void gfar_mdio_bus_name(char *name, struct device_node *np)
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{
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const u32 *reg;
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reg = of_get_property(np, "reg", NULL);
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snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0);
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}
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/* Scan the bus in reverse, looking for an empty spot */
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static int gfar_mdio_find_free(struct mii_bus *new_bus)
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{
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int i;
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for (i = PHY_MAX_ADDR; i > 0; i--) {
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u32 phy_id;
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if (get_phy_id(new_bus, i, &phy_id))
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return -1;
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if (phy_id == 0xffffffff)
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break;
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}
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return i;
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}
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static int gfar_mdio_probe(struct of_device *ofdev,
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const struct of_device_id *match)
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{
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struct gfar_mii __iomem *regs;
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struct gfar __iomem *enet_regs;
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struct mii_bus *new_bus;
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int err = 0;
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u64 addr, size;
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struct device_node *np = ofdev->node;
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struct device_node *tbi;
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int tbiaddr = -1;
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new_bus = mdiobus_alloc();
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if (NULL == new_bus)
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return -ENOMEM;
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device_init_wakeup(&ofdev->dev, 1);
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new_bus->name = "Gianfar MII Bus",
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new_bus->read = &gfar_mdio_read,
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new_bus->write = &gfar_mdio_write,
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new_bus->reset = &gfar_mdio_reset,
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gfar_mdio_bus_name(new_bus->id, np);
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/* Set the PHY base address */
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addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
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regs = ioremap(addr, size);
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if (NULL == regs) {
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err = -ENOMEM;
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goto err_free_bus;
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}
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new_bus->priv = (void __force *)regs;
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new_bus->irq = create_irq_map(np);
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if (new_bus->irq == NULL) {
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err = -ENOMEM;
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goto err_unmap_regs;
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}
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new_bus->parent = &ofdev->dev;
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dev_set_drvdata(&ofdev->dev, new_bus);
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/*
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* This is mildly evil, but so is our hardware for doing this.
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* Also, we have to cast back to struct gfar_mii because of
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* definition weirdness done in gianfar.h.
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*/
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enet_regs = (struct gfar __force __iomem *)
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((char __force *)regs - offsetof(struct gfar, gfar_mii_regs));
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for_each_child_of_node(np, tbi) {
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if (!strncmp(tbi->type, "tbi-phy", 8))
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break;
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}
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if (tbi) {
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const u32 *prop = of_get_property(tbi, "reg", NULL);
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if (prop)
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tbiaddr = *prop;
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}
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if (tbiaddr == -1) {
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gfar_write(&enet_regs->tbipa, 0);
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tbiaddr = gfar_mdio_find_free(new_bus);
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}
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/*
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* We define TBIPA at 0 to be illegal, opting to fail for boards that
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* have PHYs at 1-31, rather than change tbipa and rescan.
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*/
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if (tbiaddr == 0) {
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err = -EBUSY;
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goto err_free_irqs;
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}
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gfar_write(&enet_regs->tbipa, tbiaddr);
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/*
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* The TBIPHY-only buses will find PHYs at every address,
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* so we mask them all but the TBI
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*/
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if (!of_device_is_compatible(np, "fsl,gianfar-mdio"))
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new_bus->phy_mask = ~(1 << tbiaddr);
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err = mdiobus_register(new_bus);
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if (err != 0) {
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printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
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new_bus->name);
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goto err_free_irqs;
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}
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return 0;
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err_free_irqs:
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kfree(new_bus->irq);
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err_unmap_regs:
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iounmap(regs);
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err_free_bus:
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mdiobus_free(new_bus);
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return err;
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}
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static int gfar_mdio_remove(struct of_device *ofdev)
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{
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struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
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mdiobus_unregister(bus);
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dev_set_drvdata(&ofdev->dev, NULL);
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iounmap((void __force __iomem *)bus->priv);
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bus->priv = NULL;
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kfree(bus->irq);
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mdiobus_free(bus);
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return 0;
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}
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static struct of_device_id gfar_mdio_match[] =
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{
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{
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.compatible = "fsl,gianfar-mdio",
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},
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{
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.compatible = "fsl,gianfar-tbi",
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},
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{
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.type = "mdio",
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.compatible = "gianfar",
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},
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{},
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};
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static struct of_platform_driver gianfar_mdio_driver = {
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.name = "fsl-gianfar_mdio",
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.match_table = gfar_mdio_match,
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.probe = gfar_mdio_probe,
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.remove = gfar_mdio_remove,
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};
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int __init gfar_mdio_init(void)
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{
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return of_register_platform_driver(&gianfar_mdio_driver);
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}
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void gfar_mdio_exit(void)
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{
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of_unregister_platform_driver(&gianfar_mdio_driver);
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}
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