mirror of https://gitee.com/openkylin/linux.git
iwlegacy: rename il_{read,write}_prph
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
This commit is contained in:
Stanislaw Gruszka
parent
0c1a94e299
commit
db54eb57ce
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@ -797,18 +797,18 @@ static int il3945_tx_reset(struct il_priv *il)
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{
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/* bypass mode */
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il_write_prph(il, ALM_SCD_MODE_REG, 0x2);
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il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
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/* RA 0 is active */
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il_write_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
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il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
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/* all 6 fifo are active */
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il_write_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
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il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
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il_write_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
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il_write_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
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il_write_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
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il_write_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
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il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
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il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
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il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
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il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
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il_wr(il, FH39_TSSR_CBB_BASE,
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il->_3945.shared_phys);
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@ -878,8 +878,8 @@ static int il3945_apm_init(struct il_priv *il)
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int ret = il_apm_init(il);
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/* Clear APMG (NIC's internal power management) interrupts */
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il_write_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
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il_write_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
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il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
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il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
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/* Reset radio chip */
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il_set_bits_prph(il, APMG_PS_CTRL_REG,
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@ -1025,8 +1025,8 @@ void il3945_hw_txq_ctx_stop(struct il_priv *il)
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int txq_id;
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/* stop SCD */
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il_write_prph(il, ALM_SCD_MODE_REG, 0);
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il_write_prph(il, ALM_SCD_TXFACT_REG, 0);
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il_wr_prph(il, ALM_SCD_MODE_REG, 0);
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il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
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/* reset TFD queues */
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for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
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@ -2475,11 +2475,11 @@ static int il3945_verify_bsm(struct il_priv *il)
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D_INFO("Begin verify bsm\n");
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/* verify BSM SRAM contents */
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val = il_read_prph(il, BSM_WR_DWCOUNT_REG);
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val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
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for (reg = BSM_SRAM_LOWER_BOUND;
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reg < BSM_SRAM_LOWER_BOUND + len;
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reg += sizeof(u32), image++) {
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val = il_read_prph(il, reg);
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val = il_rd_prph(il, reg);
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if (val != le32_to_cpu(*image)) {
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IL_ERR("BSM uCode verification failed at "
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"addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
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@ -2583,16 +2583,16 @@ static int il3945_load_bsm(struct il_priv *il)
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inst_len = il->ucode_init.len;
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data_len = il->ucode_init_data.len;
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il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
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il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
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il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
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il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
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/* Fill BSM memory with bootstrap instructions */
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for (reg_offset = BSM_SRAM_LOWER_BOUND;
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reg_offset < BSM_SRAM_LOWER_BOUND + len;
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reg_offset += sizeof(u32), image++)
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_il_write_prph(il, reg_offset,
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_il_wr_prph(il, reg_offset,
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le32_to_cpu(*image));
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rc = il3945_verify_bsm(il);
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@ -2600,19 +2600,19 @@ static int il3945_load_bsm(struct il_priv *il)
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return rc;
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/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
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il_write_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
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il_write_prph(il, BSM_WR_MEM_DST_REG,
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il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
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il_wr_prph(il, BSM_WR_MEM_DST_REG,
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IWL39_RTC_INST_LOWER_BOUND);
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il_write_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
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il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
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/* Load bootstrap code into instruction SRAM now,
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* to prepare to load "initialize" uCode */
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il_write_prph(il, BSM_WR_CTRL_REG,
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il_wr_prph(il, BSM_WR_CTRL_REG,
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BSM_WR_CTRL_REG_BIT_START);
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/* Wait for load of bootstrap uCode to finish */
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for (i = 0; i < 100; i++) {
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done = il_read_prph(il, BSM_WR_CTRL_REG);
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done = il_rd_prph(il, BSM_WR_CTRL_REG);
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if (!(done & BSM_WR_CTRL_REG_BIT_START))
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break;
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udelay(10);
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@ -2626,7 +2626,7 @@ static int il3945_load_bsm(struct il_priv *il)
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/* Enable future boot loads whenever power management unit triggers it
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* (e.g. when powering back up after power-save shutdown) */
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il_write_prph(il, BSM_WR_CTRL_REG,
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il_wr_prph(il, BSM_WR_CTRL_REG,
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BSM_WR_CTRL_REG_BIT_START_EN);
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return 0;
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@ -754,7 +754,7 @@ static void il4965_tx_queue_stop_scheduler(struct il_priv *il,
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{
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/* Simply stop the queue, but don't change any configuration;
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* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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il_write_prph(il,
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il_wr_prph(il,
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IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
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(0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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(1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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@ -72,11 +72,11 @@ static int il4965_verify_bsm(struct il_priv *il)
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D_INFO("Begin verify bsm\n");
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/* verify BSM SRAM contents */
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val = il_read_prph(il, BSM_WR_DWCOUNT_REG);
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val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
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for (reg = BSM_SRAM_LOWER_BOUND;
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reg < BSM_SRAM_LOWER_BOUND + len;
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reg += sizeof(u32), image++) {
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val = il_read_prph(il, reg);
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val = il_rd_prph(il, reg);
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if (val != le32_to_cpu(*image)) {
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IL_ERR("BSM uCode verification failed at "
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"addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
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@ -156,34 +156,34 @@ static int il4965_load_bsm(struct il_priv *il)
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inst_len = il->ucode_init.len;
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data_len = il->ucode_init_data.len;
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il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
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il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
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il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
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il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
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/* Fill BSM memory with bootstrap instructions */
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for (reg_offset = BSM_SRAM_LOWER_BOUND;
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reg_offset < BSM_SRAM_LOWER_BOUND + len;
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reg_offset += sizeof(u32), image++)
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_il_write_prph(il, reg_offset, le32_to_cpu(*image));
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_il_wr_prph(il, reg_offset, le32_to_cpu(*image));
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ret = il4965_verify_bsm(il);
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if (ret)
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return ret;
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/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
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il_write_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
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il_write_prph(il,
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il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
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il_wr_prph(il,
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BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
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il_write_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
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il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
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/* Load bootstrap code into instruction SRAM now,
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* to prepare to load "initialize" uCode */
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il_write_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
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il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
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/* Wait for load of bootstrap uCode to finish */
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for (i = 0; i < 100; i++) {
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done = il_read_prph(il, BSM_WR_CTRL_REG);
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done = il_rd_prph(il, BSM_WR_CTRL_REG);
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if (!(done & BSM_WR_CTRL_REG_BIT_START))
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break;
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udelay(10);
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@ -197,7 +197,7 @@ static int il4965_load_bsm(struct il_priv *il)
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/* Enable future boot loads whenever power management unit triggers it
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* (e.g. when powering back up after power-save shutdown) */
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il_write_prph(il,
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il_wr_prph(il,
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BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
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@ -224,14 +224,14 @@ static int il4965_set_ucode_ptrs(struct il_priv *il)
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pdata = il->ucode_data_backup.p_addr >> 4;
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/* Tell bootstrap uCode where to find image to load */
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il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
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il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
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il->ucode_data.len);
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/* Inst byte count must be last to set up, bit 31 signals uCode
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* that all new ptr/size info is in place */
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il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
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il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
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il->ucode_code.len | BSM_DRAM_INST_LOAD);
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D_INFO("Runtime uCode pointers are set.\n");
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@ -1069,7 +1069,7 @@ int il_apm_init(struct il_priv *il)
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is supported, e.g. il_write_prph()
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* device-internal resources is supported, e.g. il_wr_prph()
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* and accesses to uCode SRAM.
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*/
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ret = _il_poll_bit(il, CSR_GP_CNTRL,
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@ -1089,10 +1089,10 @@ int il_apm_init(struct il_priv *il)
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* set by default in "CLK_CTRL_REG" after reset.
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*/
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if (il->cfg->base_params->use_bsm)
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il_write_prph(il, APMG_CLK_EN_REG,
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il_wr_prph(il, APMG_CLK_EN_REG,
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APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
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else
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il_write_prph(il, APMG_CLK_EN_REG,
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il_wr_prph(il, APMG_CLK_EN_REG,
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APMG_CLK_VAL_DMA_CLK_RQT);
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udelay(20);
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@ -197,26 +197,27 @@ static inline int il_poll_bit(struct il_priv *il, u32 addr,
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return -ETIMEDOUT;
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}
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static inline u32 _il_read_prph(struct il_priv *il, u32 reg)
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static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
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{
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_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
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rmb();
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return _il_rd(il, HBUS_TARG_PRPH_RDAT);
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}
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static inline u32 il_read_prph(struct il_priv *il, u32 reg)
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static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
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{
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unsigned long reg_flags;
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u32 val;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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val = _il_read_prph(il, reg);
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val = _il_rd_prph(il, reg);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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return val;
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}
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static inline void _il_write_prph(struct il_priv *il,
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static inline void _il_wr_prph(struct il_priv *il,
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u32 addr, u32 val)
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{
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_il_wr(il, HBUS_TARG_PRPH_WADDR,
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@ -226,20 +227,20 @@ static inline void _il_write_prph(struct il_priv *il,
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}
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static inline void
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il_write_prph(struct il_priv *il, u32 addr, u32 val)
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il_wr_prph(struct il_priv *il, u32 addr, u32 val)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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if (!_il_grab_nic_access(il)) {
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_il_write_prph(il, addr, val);
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_il_wr_prph(il, addr, val);
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_il_release_nic_access(il);
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}
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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#define _il_set_bits_prph(il, reg, mask) \
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_il_write_prph(il, reg, (_il_read_prph(il, reg) | mask))
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_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
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static inline void
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il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
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@ -254,8 +255,8 @@ il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
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}
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#define _il_set_bits_mask_prph(il, reg, bits, mask) \
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_il_write_prph(il, reg, \
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((_il_read_prph(il, reg) & mask) | bits))
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_il_wr_prph(il, reg, \
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((_il_rd_prph(il, reg) & mask) | bits))
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static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
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u32 bits, u32 mask)
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@ -277,8 +278,8 @@ static inline void il_clear_bits_prph(struct il_priv
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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val = _il_read_prph(il, reg);
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_il_write_prph(il, reg, (val & ~mask));
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val = _il_rd_prph(il, reg);
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_il_wr_prph(il, reg, (val & ~mask));
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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@ -2122,14 +2122,14 @@ static int il3945_set_ucode_ptrs(struct il_priv *il)
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pdata = il->ucode_data_backup.p_addr;
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/* Tell bootstrap uCode where to find image to load */
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il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
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il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
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il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
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il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
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il->ucode_data.len);
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/* Inst byte count must be last to set up, bit 31 signals uCode
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* that all new ptr/size info is in place */
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il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
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il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
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il->ucode_code.len | BSM_DRAM_INST_LOAD);
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D_INFO("Runtime uCode pointers are set.\n");
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@ -2210,7 +2210,7 @@ static void il3945_alive_start(struct il_priv *il)
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goto restart;
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}
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rfkill = il_read_prph(il, APMG_RFKILL_REG);
|
||||
rfkill = il_rd_prph(il, APMG_RFKILL_REG);
|
||||
D_INFO("RFKILL status: 0x%x\n", rfkill);
|
||||
|
||||
if (rfkill & 0x1) {
|
||||
|
|
@ -2342,7 +2342,7 @@ static void __il3945_down(struct il_priv *il)
|
|||
il3945_hw_rxq_stop(il);
|
||||
|
||||
/* Power-down device's busmaster DMA clocks */
|
||||
il_write_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
|
||||
il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
|
||||
udelay(5);
|
||||
|
||||
/* Stop the device, and put it in low power state */
|
||||
|
|
|
|||
|
|
@ -1622,7 +1622,7 @@ static int il4965_alive_notify(struct il_priv *il)
|
|||
spin_lock_irqsave(&il->lock, flags);
|
||||
|
||||
/* Clear 4965's internal Tx Scheduler data base */
|
||||
il->scd_base_addr = il_read_prph(il,
|
||||
il->scd_base_addr = il_rd_prph(il,
|
||||
IWL49_SCD_SRAM_BASE_ADDR);
|
||||
a = il->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
|
||||
for (; a < il->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
|
||||
|
|
@ -1634,7 +1634,7 @@ static int il4965_alive_notify(struct il_priv *il)
|
|||
il_write_targ_mem(il, a, 0);
|
||||
|
||||
/* Tel 4965 where to find Tx byte count tables */
|
||||
il_write_prph(il, IWL49_SCD_DRAM_BASE_ADDR,
|
||||
il_wr_prph(il, IWL49_SCD_DRAM_BASE_ADDR,
|
||||
il->scd_bc_tbls.dma >> 10);
|
||||
|
||||
/* Enable DMA channel */
|
||||
|
|
@ -1650,13 +1650,13 @@ static int il4965_alive_notify(struct il_priv *il)
|
|||
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
|
||||
|
||||
/* Disable chain mode for all queues */
|
||||
il_write_prph(il, IWL49_SCD_QUEUECHAIN_SEL, 0);
|
||||
il_wr_prph(il, IWL49_SCD_QUEUECHAIN_SEL, 0);
|
||||
|
||||
/* Initialize each Tx queue (including the command queue) */
|
||||
for (i = 0; i < il->hw_params.max_txq_num; i++) {
|
||||
|
||||
/* TFD circular buffer read/write indexes */
|
||||
il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(i), 0);
|
||||
il_wr_prph(il, IWL49_SCD_QUEUE_RDPTR(i), 0);
|
||||
il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
|
||||
|
||||
/* Max Tx Window size for Scheduler-ACK mode */
|
||||
|
|
@ -1675,7 +1675,7 @@ static int il4965_alive_notify(struct il_priv *il)
|
|||
IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
|
||||
|
||||
}
|
||||
il_write_prph(il, IWL49_SCD_INTERRUPT_MASK,
|
||||
il_wr_prph(il, IWL49_SCD_INTERRUPT_MASK,
|
||||
(1 << il->hw_params.max_txq_num) - 1);
|
||||
|
||||
/* Activate all Tx DMA/FIFO channels */
|
||||
|
|
@ -1868,7 +1868,7 @@ static void __il4965_down(struct il_priv *il)
|
|||
il4965_rxq_stop(il);
|
||||
|
||||
/* Power-down device's busmaster DMA clocks */
|
||||
il_write_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
|
||||
il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
|
||||
udelay(5);
|
||||
|
||||
/* Make sure (redundant) we've released our request to stay awake */
|
||||
|
|
@ -2733,7 +2733,7 @@ void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 index)
|
|||
{
|
||||
il_wr(il, HBUS_TARG_WRPTR,
|
||||
(index & 0xff) | (txq_id << 8));
|
||||
il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
|
||||
il_wr_prph(il, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
|
||||
}
|
||||
|
||||
void il4965_tx_queue_set_status(struct il_priv *il,
|
||||
|
|
@ -2746,7 +2746,7 @@ void il4965_tx_queue_set_status(struct il_priv *il,
|
|||
int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
|
||||
|
||||
/* Set up and activate */
|
||||
il_write_prph(il, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
|
||||
il_wr_prph(il, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
|
||||
(active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
|
||||
(tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
|
||||
(scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
|
||||
|
|
@ -3195,7 +3195,7 @@ static void __devexit il4965_pci_remove(struct pci_dev *pdev)
|
|||
*/
|
||||
void il4965_txq_set_sched(struct il_priv *il, u32 mask)
|
||||
{
|
||||
il_write_prph(il, IWL49_SCD_TXFACT, mask);
|
||||
il_wr_prph(il, IWL49_SCD_TXFACT, mask);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue