mirror of https://gitee.com/openkylin/linux.git
Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: "These are the ARM BPF fixes as discussed earlier this week" * 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: net: bpf: clarify tail_call index ARM: net: bpf: fix LDX instructions ARM: net: bpf: fix register saving ARM: net: bpf: correct stack layout documentation ARM: net: bpf: move stack documentation ARM: net: bpf: fix stack alignment ARM: net: bpf: fix tail call jumps ARM: net: bpf: avoid 'bx' instruction on non-Thumb capable CPUs
This commit is contained in:
Linus Torvalds
commit
dda3e15231
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|
@ -27,14 +27,58 @@
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|||
|
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int bpf_jit_enable __read_mostly;
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||||
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/*
|
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* eBPF prog stack layout:
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*
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* high
|
||||
* original ARM_SP => +-----+
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* | | callee saved registers
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||||
* +-----+ <= (BPF_FP + SCRATCH_SIZE)
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* | ... | eBPF JIT scratch space
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* eBPF fp register => +-----+
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* (BPF_FP) | ... | eBPF prog stack
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||||
* +-----+
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* |RSVD | JIT scratchpad
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* current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
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* | |
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* | ... | Function call stack
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* | |
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* +-----+
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* low
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*
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* The callee saved registers depends on whether frame pointers are enabled.
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* With frame pointers (to be compliant with the ABI):
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*
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* high
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* original ARM_SP => +------------------+ \
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* | pc | |
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* current ARM_FP => +------------------+ } callee saved registers
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* |r4-r8,r10,fp,ip,lr| |
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* +------------------+ /
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* low
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*
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* Without frame pointers:
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*
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* high
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* original ARM_SP => +------------------+
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* | r4-r8,r10,fp,lr | callee saved registers
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* current ARM_FP => +------------------+
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* low
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*
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* When popping registers off the stack at the end of a BPF function, we
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* reference them via the current ARM_FP register.
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*/
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#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
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1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R10 | \
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1 << ARM_FP)
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#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
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#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
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#define STACK_OFFSET(k) (k)
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#define TMP_REG_1 (MAX_BPF_JIT_REG + 0) /* TEMP Register 1 */
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1) /* TEMP Register 2 */
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#define TCALL_CNT (MAX_BPF_JIT_REG + 2) /* Tail Call Count */
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/* Flags used for JIT optimization */
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#define SEEN_CALL (1 << 0)
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#define FLAG_IMM_OVERFLOW (1 << 0)
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/*
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@ -95,7 +139,6 @@ static const u8 bpf2a32[][2] = {
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* idx : index of current last JITed instruction.
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* prologue_bytes : bytes used in prologue.
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* epilogue_offset : offset of epilogue starting.
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* seen : bit mask used for JIT optimization.
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* offsets : array of eBPF instruction offsets in
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* JITed code.
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* target : final JITed code.
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@ -110,7 +153,6 @@ struct jit_ctx {
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unsigned int idx;
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unsigned int prologue_bytes;
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unsigned int epilogue_offset;
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u32 seen;
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u32 flags;
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u32 *offsets;
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u32 *target;
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@ -179,8 +221,13 @@ static void jit_fill_hole(void *area, unsigned int size)
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*ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
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}
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/* Stack must be multiples of 16 Bytes */
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#define STACK_ALIGN(sz) (((sz) + 3) & ~3)
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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/* EABI requires the stack to be aligned to 64-bit boundaries */
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#define STACK_ALIGNMENT 8
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#else
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/* Stack must be aligned to 32-bit boundaries */
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#define STACK_ALIGNMENT 4
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#endif
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/* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4,
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* BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9,
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@ -194,7 +241,7 @@ static void jit_fill_hole(void *area, unsigned int size)
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+ SCRATCH_SIZE + \
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+ 4 /* extra for skb_copy_bits buffer */)
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#define STACK_SIZE STACK_ALIGN(_STACK_SIZE)
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#define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
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/* Get the offset of eBPF REGISTERs stored on scratch space. */
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#define STACK_VAR(off) (STACK_SIZE-off-4)
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|
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@ -285,16 +332,19 @@ static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
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emit_mov_i_no8m(rd, val, ctx);
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}
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static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
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static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
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{
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ctx->seen |= SEEN_CALL;
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#if __LINUX_ARM_ARCH__ < 5
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emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
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if (elf_hwcap & HWCAP_THUMB)
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emit(ARM_BX(tgt_reg), ctx);
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else
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emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
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}
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static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
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{
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#if __LINUX_ARM_ARCH__ < 5
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emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
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emit_bx_r(tgt_reg, ctx);
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#else
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emit(ARM_BLX_R(tgt_reg), ctx);
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#endif
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@ -354,7 +404,6 @@ static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
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}
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/* Call appropriate function */
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ctx->seen |= SEEN_CALL;
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emit_mov_i(ARM_IP, op == BPF_DIV ?
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(u32)jit_udiv32 : (u32)jit_mod32, ctx);
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emit_blx_r(ARM_IP, ctx);
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@ -620,8 +669,6 @@ static inline void emit_a32_lsh_r64(const u8 dst[], const u8 src[], bool dstk,
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/* Do LSH operation */
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emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
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emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
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/* As we are using ARM_LR */
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ctx->seen |= SEEN_CALL;
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emit(ARM_MOV_SR(ARM_LR, rm, SRTYPE_ASL, rt), ctx);
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emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd, SRTYPE_ASL, ARM_IP), ctx);
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emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd, SRTYPE_LSR, tmp2[0]), ctx);
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@ -656,8 +703,6 @@ static inline void emit_a32_arsh_r64(const u8 dst[], const u8 src[], bool dstk,
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/* Do the ARSH operation */
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emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
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emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
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/* As we are using ARM_LR */
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ctx->seen |= SEEN_CALL;
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emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx);
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emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx);
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_emit(ARM_COND_MI, ARM_B(0), ctx);
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@ -692,8 +737,6 @@ static inline void emit_a32_lsr_r64(const u8 dst[], const u8 src[], bool dstk,
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/* Do LSH operation */
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emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
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emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
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/* As we are using ARM_LR */
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ctx->seen |= SEEN_CALL;
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emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx);
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emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx);
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emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_LSR, tmp2[0]), ctx);
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@ -828,8 +871,6 @@ static inline void emit_a32_mul_r64(const u8 dst[], const u8 src[], bool dstk,
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/* Do Multiplication */
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emit(ARM_MUL(ARM_IP, rd, rn), ctx);
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emit(ARM_MUL(ARM_LR, rm, rt), ctx);
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/* As we are using ARM_LR */
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ctx->seen |= SEEN_CALL;
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emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
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emit(ARM_UMULL(ARM_IP, rm, rd, rt), ctx);
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@ -872,33 +913,53 @@ static inline void emit_str_r(const u8 dst, const u8 src, bool dstk,
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}
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/* dst = *(size*)(src + off) */
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static inline void emit_ldx_r(const u8 dst, const u8 src, bool dstk,
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const s32 off, struct jit_ctx *ctx, const u8 sz){
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static inline void emit_ldx_r(const u8 dst[], const u8 src, bool dstk,
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s32 off, struct jit_ctx *ctx, const u8 sz){
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const u8 *tmp = bpf2a32[TMP_REG_1];
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u8 rd = dstk ? tmp[1] : dst;
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const u8 *rd = dstk ? tmp : dst;
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u8 rm = src;
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s32 off_max;
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if (off) {
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if (sz == BPF_H)
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off_max = 0xff;
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else
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off_max = 0xfff;
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if (off < 0 || off > off_max) {
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emit_a32_mov_i(tmp[0], off, false, ctx);
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emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
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rm = tmp[0];
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off = 0;
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} else if (rd[1] == rm) {
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emit(ARM_MOV_R(tmp[0], rm), ctx);
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rm = tmp[0];
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}
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switch (sz) {
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case BPF_W:
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/* Load a Word */
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emit(ARM_LDR_I(rd, rm, 0), ctx);
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case BPF_B:
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/* Load a Byte */
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emit(ARM_LDRB_I(rd[1], rm, off), ctx);
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emit_a32_mov_i(dst[0], 0, dstk, ctx);
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break;
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case BPF_H:
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/* Load a HalfWord */
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emit(ARM_LDRH_I(rd, rm, 0), ctx);
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emit(ARM_LDRH_I(rd[1], rm, off), ctx);
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emit_a32_mov_i(dst[0], 0, dstk, ctx);
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break;
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case BPF_B:
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/* Load a Byte */
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emit(ARM_LDRB_I(rd, rm, 0), ctx);
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case BPF_W:
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/* Load a Word */
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emit(ARM_LDR_I(rd[1], rm, off), ctx);
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emit_a32_mov_i(dst[0], 0, dstk, ctx);
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break;
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case BPF_DW:
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/* Load a Double Word */
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emit(ARM_LDR_I(rd[1], rm, off), ctx);
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emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
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break;
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}
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if (dstk)
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emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst)), ctx);
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emit(ARM_STR_I(rd[1], ARM_SP, STACK_VAR(dst[1])), ctx);
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if (dstk && sz == BPF_DW)
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emit(ARM_STR_I(rd[0], ARM_SP, STACK_VAR(dst[0])), ctx);
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}
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|
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/* Arithmatic Operation */
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|
|
@ -906,7 +967,6 @@ static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
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const u8 rn, struct jit_ctx *ctx, u8 op) {
|
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switch (op) {
|
||||
case BPF_JSET:
|
||||
ctx->seen |= SEEN_CALL;
|
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emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
|
||||
emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
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emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
|
||||
|
|
@ -945,7 +1005,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
|
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const u8 *tcc = bpf2a32[TCALL_CNT];
|
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const int idx0 = ctx->idx;
|
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#define cur_offset (ctx->idx - idx0)
|
||||
#define jmp_offset (out_offset - (cur_offset))
|
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#define jmp_offset (out_offset - (cur_offset) - 2)
|
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u32 off, lo, hi;
|
||||
|
||||
/* if (index >= array->map.max_entries)
|
||||
|
|
@ -956,7 +1016,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
|
|||
emit_a32_mov_i(tmp[1], off, false, ctx);
|
||||
emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r2[1])), ctx);
|
||||
emit(ARM_LDR_R(tmp[1], tmp2[1], tmp[1]), ctx);
|
||||
/* index (64 bit) */
|
||||
/* index is 32-bit for arrays */
|
||||
emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r3[1])), ctx);
|
||||
/* index >= array->map.max_entries */
|
||||
emit(ARM_CMP_R(tmp2[1], tmp[1]), ctx);
|
||||
|
|
@ -997,7 +1057,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
|
|||
emit_a32_mov_i(tmp2[1], off, false, ctx);
|
||||
emit(ARM_LDR_R(tmp[1], tmp[1], tmp2[1]), ctx);
|
||||
emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
|
||||
emit(ARM_BX(tmp[1]), ctx);
|
||||
emit_bx_r(tmp[1], ctx);
|
||||
|
||||
/* out: */
|
||||
if (out_offset == -1)
|
||||
|
|
@ -1070,54 +1130,22 @@ static void build_prologue(struct jit_ctx *ctx)
|
|||
const u8 r2 = bpf2a32[BPF_REG_1][1];
|
||||
const u8 r3 = bpf2a32[BPF_REG_1][0];
|
||||
const u8 r4 = bpf2a32[BPF_REG_6][1];
|
||||
const u8 r5 = bpf2a32[BPF_REG_6][0];
|
||||
const u8 r6 = bpf2a32[TMP_REG_1][1];
|
||||
const u8 r7 = bpf2a32[TMP_REG_1][0];
|
||||
const u8 r8 = bpf2a32[TMP_REG_2][1];
|
||||
const u8 r10 = bpf2a32[TMP_REG_2][0];
|
||||
const u8 fplo = bpf2a32[BPF_REG_FP][1];
|
||||
const u8 fphi = bpf2a32[BPF_REG_FP][0];
|
||||
const u8 sp = ARM_SP;
|
||||
const u8 *tcc = bpf2a32[TCALL_CNT];
|
||||
|
||||
u16 reg_set = 0;
|
||||
|
||||
/*
|
||||
* eBPF prog stack layout
|
||||
*
|
||||
* high
|
||||
* original ARM_SP => +-----+ eBPF prologue
|
||||
* |FP/LR|
|
||||
* current ARM_FP => +-----+
|
||||
* | ... | callee saved registers
|
||||
* eBPF fp register => +-----+ <= (BPF_FP)
|
||||
* | ... | eBPF JIT scratch space
|
||||
* | | eBPF prog stack
|
||||
* +-----+
|
||||
* |RSVD | JIT scratchpad
|
||||
* current A64_SP => +-----+ <= (BPF_FP - STACK_SIZE)
|
||||
* | |
|
||||
* | ... | Function call stack
|
||||
* | |
|
||||
* +-----+
|
||||
* low
|
||||
*/
|
||||
|
||||
/* Save callee saved registers. */
|
||||
reg_set |= (1<<r4) | (1<<r5) | (1<<r6) | (1<<r7) | (1<<r8) | (1<<r10);
|
||||
#ifdef CONFIG_FRAME_POINTER
|
||||
reg_set |= (1<<ARM_FP) | (1<<ARM_IP) | (1<<ARM_LR) | (1<<ARM_PC);
|
||||
emit(ARM_MOV_R(ARM_IP, sp), ctx);
|
||||
u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
|
||||
emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
|
||||
emit(ARM_PUSH(reg_set), ctx);
|
||||
emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
|
||||
#else
|
||||
/* Check if call instruction exists in BPF body */
|
||||
if (ctx->seen & SEEN_CALL)
|
||||
reg_set |= (1<<ARM_LR);
|
||||
emit(ARM_PUSH(reg_set), ctx);
|
||||
emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
|
||||
emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
|
||||
#endif
|
||||
/* Save frame pointer for later */
|
||||
emit(ARM_SUB_I(ARM_IP, sp, SCRATCH_SIZE), ctx);
|
||||
emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx);
|
||||
|
||||
ctx->stack_size = imm8m(STACK_SIZE);
|
||||
|
||||
|
|
@ -1140,33 +1168,19 @@ static void build_prologue(struct jit_ctx *ctx)
|
|||
/* end of prologue */
|
||||
}
|
||||
|
||||
/* restore callee saved registers. */
|
||||
static void build_epilogue(struct jit_ctx *ctx)
|
||||
{
|
||||
const u8 r4 = bpf2a32[BPF_REG_6][1];
|
||||
const u8 r5 = bpf2a32[BPF_REG_6][0];
|
||||
const u8 r6 = bpf2a32[TMP_REG_1][1];
|
||||
const u8 r7 = bpf2a32[TMP_REG_1][0];
|
||||
const u8 r8 = bpf2a32[TMP_REG_2][1];
|
||||
const u8 r10 = bpf2a32[TMP_REG_2][0];
|
||||
u16 reg_set = 0;
|
||||
|
||||
/* unwind function call stack */
|
||||
emit(ARM_ADD_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
|
||||
|
||||
/* restore callee saved registers. */
|
||||
reg_set |= (1<<r4) | (1<<r5) | (1<<r6) | (1<<r7) | (1<<r8) | (1<<r10);
|
||||
#ifdef CONFIG_FRAME_POINTER
|
||||
/* the first instruction of the prologue was: mov ip, sp */
|
||||
reg_set |= (1<<ARM_FP) | (1<<ARM_SP) | (1<<ARM_PC);
|
||||
/* When using frame pointers, some additional registers need to
|
||||
* be loaded. */
|
||||
u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
|
||||
emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
|
||||
emit(ARM_LDM(ARM_SP, reg_set), ctx);
|
||||
#else
|
||||
if (ctx->seen & SEEN_CALL)
|
||||
reg_set |= (1<<ARM_PC);
|
||||
/* Restore callee saved registers. */
|
||||
emit(ARM_POP(reg_set), ctx);
|
||||
/* Return back to the callee function */
|
||||
if (!(ctx->seen & SEEN_CALL))
|
||||
emit(ARM_BX(ARM_LR), ctx);
|
||||
emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
|
||||
emit(ARM_POP(CALLEE_POP_MASK), ctx);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1394,8 +1408,6 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
|
|||
emit_rev32(rt, rt, ctx);
|
||||
goto emit_bswap_uxt;
|
||||
case 64:
|
||||
/* Because of the usage of ARM_LR */
|
||||
ctx->seen |= SEEN_CALL;
|
||||
emit_rev32(ARM_LR, rt, ctx);
|
||||
emit_rev32(rt, rd, ctx);
|
||||
emit(ARM_MOV_R(rd, ARM_LR), ctx);
|
||||
|
|
@ -1448,22 +1460,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
|
|||
rn = sstk ? tmp2[1] : src_lo;
|
||||
if (sstk)
|
||||
emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx);
|
||||
switch (BPF_SIZE(code)) {
|
||||
case BPF_W:
|
||||
/* Load a Word */
|
||||
case BPF_H:
|
||||
/* Load a Half-Word */
|
||||
case BPF_B:
|
||||
/* Load a Byte */
|
||||
emit_ldx_r(dst_lo, rn, dstk, off, ctx, BPF_SIZE(code));
|
||||
emit_a32_mov_i(dst_hi, 0, dstk, ctx);
|
||||
break;
|
||||
case BPF_DW:
|
||||
/* Load a double word */
|
||||
emit_ldx_r(dst_lo, rn, dstk, off, ctx, BPF_W);
|
||||
emit_ldx_r(dst_hi, rn, dstk, off+4, ctx, BPF_W);
|
||||
break;
|
||||
}
|
||||
emit_ldx_r(dst, rn, dstk, off, ctx, BPF_SIZE(code));
|
||||
break;
|
||||
/* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
|
||||
case BPF_LD | BPF_ABS | BPF_W:
|
||||
|
|
|
|||
Loading…
Reference in New Issue