mirror of https://gitee.com/openkylin/linux.git
drm/i915: Disable primary plane trickle feed for g4x
The docs say that the trickle feed disable bit is present (for primary planes only, not video sprites) on CTG, and that it must be set for ELK. Just set it for all g4x chipsets. v2: Do it in init_clock_gating too Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1958,6 +1958,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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dspcntr &= ~DISPPLANE_TILED;
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dspcntr &= ~DISPPLANE_TILED;
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}
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}
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if (IS_G4X(dev))
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dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
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I915_WRITE(reg, dspcntr);
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I915_WRITE(reg, dspcntr);
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linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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@ -4908,6 +4908,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dspclk_gate;
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uint32_t dspclk_gate;
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int pipe;
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I915_WRITE(RENCLK_GATE_D1, 0);
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I915_WRITE(RENCLK_GATE_D1, 0);
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I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
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I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
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@ -4924,6 +4925,14 @@ static void g4x_init_clock_gating(struct drm_device *dev)
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/* WaDisableRenderCachePipelinedFlush */
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/* WaDisableRenderCachePipelinedFlush */
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I915_WRITE(CACHE_MODE_0,
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I915_WRITE(CACHE_MODE_0,
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_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
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_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
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for_each_pipe(pipe) {
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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DISPPLANE_TRICKLE_FEED_DISABLE);
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intel_flush_display_plane(dev_priv, pipe);
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}
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}
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}
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static void crestline_init_clock_gating(struct drm_device *dev)
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static void crestline_init_clock_gating(struct drm_device *dev)
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