mirror of https://gitee.com/openkylin/linux.git
clocksource: sh_tmu: Split channel fields from sh_tmu_priv
Create a new sh_tmu_channel structure to hold the channel-specific field in preparation for multiple channels per device support. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
parent
1c56cf6b04
commit
de2d12c7e8
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@ -35,11 +35,13 @@
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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struct sh_tmu_priv {
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void __iomem *mapbase;
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struct clk *clk;
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struct sh_tmu_priv;
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struct sh_tmu_channel {
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struct sh_tmu_priv *tmu;
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int irq;
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struct platform_device *pdev;
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unsigned long rate;
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unsigned long periodic;
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struct clock_event_device ced;
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@ -48,6 +50,15 @@ struct sh_tmu_priv {
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unsigned int enable_count;
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};
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struct sh_tmu_priv {
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struct platform_device *pdev;
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void __iomem *mapbase;
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struct clk *clk;
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struct sh_tmu_channel channel;
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};
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static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
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#define TSTR -1 /* shared register */
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@ -55,10 +66,10 @@ static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
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#define TCNT 1 /* channel register */
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#define TCR 2 /* channel register */
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static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
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static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
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void __iomem *base = ch->tmu->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR)
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@ -72,11 +83,11 @@ static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
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return ioread32(base + offs);
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}
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static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
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static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
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unsigned long value)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
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void __iomem *base = ch->tmu->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR) {
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@ -92,152 +103,152 @@ static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
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iowrite32(value, base + offs);
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}
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static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
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static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_tmu_lock, flags);
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value = sh_tmu_read(p, TSTR);
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value = sh_tmu_read(ch, TSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_tmu_write(p, TSTR, value);
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sh_tmu_write(ch, TSTR, value);
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raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
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}
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static int __sh_tmu_enable(struct sh_tmu_priv *p)
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static int __sh_tmu_enable(struct sh_tmu_channel *ch)
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{
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int ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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ret = clk_enable(ch->tmu->clk);
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if (ret) {
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dev_err(&p->pdev->dev, "cannot enable clock\n");
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dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n");
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return ret;
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}
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/* make sure channel is disabled */
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sh_tmu_start_stop_ch(p, 0);
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sh_tmu_start_stop_ch(ch, 0);
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/* maximum timeout */
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sh_tmu_write(p, TCOR, 0xffffffff);
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sh_tmu_write(p, TCNT, 0xffffffff);
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sh_tmu_write(ch, TCOR, 0xffffffff);
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sh_tmu_write(ch, TCNT, 0xffffffff);
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/* configure channel to parent clock / 4, irq off */
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p->rate = clk_get_rate(p->clk) / 4;
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sh_tmu_write(p, TCR, 0x0000);
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ch->rate = clk_get_rate(ch->tmu->clk) / 4;
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sh_tmu_write(ch, TCR, 0x0000);
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/* enable channel */
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sh_tmu_start_stop_ch(p, 1);
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sh_tmu_start_stop_ch(ch, 1);
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return 0;
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}
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static int sh_tmu_enable(struct sh_tmu_priv *p)
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static int sh_tmu_enable(struct sh_tmu_channel *ch)
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{
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if (p->enable_count++ > 0)
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if (ch->enable_count++ > 0)
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return 0;
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pm_runtime_get_sync(&p->pdev->dev);
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dev_pm_syscore_device(&p->pdev->dev, true);
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pm_runtime_get_sync(&ch->tmu->pdev->dev);
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dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
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return __sh_tmu_enable(p);
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return __sh_tmu_enable(ch);
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}
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static void __sh_tmu_disable(struct sh_tmu_priv *p)
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static void __sh_tmu_disable(struct sh_tmu_channel *ch)
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{
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/* disable channel */
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sh_tmu_start_stop_ch(p, 0);
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sh_tmu_start_stop_ch(ch, 0);
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/* disable interrupts in TMU block */
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sh_tmu_write(p, TCR, 0x0000);
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sh_tmu_write(ch, TCR, 0x0000);
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/* stop clock */
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clk_disable(p->clk);
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clk_disable(ch->tmu->clk);
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}
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static void sh_tmu_disable(struct sh_tmu_priv *p)
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static void sh_tmu_disable(struct sh_tmu_channel *ch)
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{
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if (WARN_ON(p->enable_count == 0))
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if (WARN_ON(ch->enable_count == 0))
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return;
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if (--p->enable_count > 0)
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if (--ch->enable_count > 0)
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return;
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__sh_tmu_disable(p);
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__sh_tmu_disable(ch);
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dev_pm_syscore_device(&p->pdev->dev, false);
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pm_runtime_put(&p->pdev->dev);
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dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
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pm_runtime_put(&ch->tmu->pdev->dev);
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}
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static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
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static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
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int periodic)
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{
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/* stop timer */
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sh_tmu_start_stop_ch(p, 0);
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sh_tmu_start_stop_ch(ch, 0);
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/* acknowledge interrupt */
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sh_tmu_read(p, TCR);
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sh_tmu_read(ch, TCR);
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/* enable interrupt */
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sh_tmu_write(p, TCR, 0x0020);
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sh_tmu_write(ch, TCR, 0x0020);
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/* reload delta value in case of periodic timer */
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if (periodic)
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sh_tmu_write(p, TCOR, delta);
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sh_tmu_write(ch, TCOR, delta);
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else
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sh_tmu_write(p, TCOR, 0xffffffff);
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sh_tmu_write(ch, TCOR, 0xffffffff);
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sh_tmu_write(p, TCNT, delta);
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sh_tmu_write(ch, TCNT, delta);
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/* start timer */
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sh_tmu_start_stop_ch(p, 1);
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sh_tmu_start_stop_ch(ch, 1);
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}
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static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
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{
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struct sh_tmu_priv *p = dev_id;
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struct sh_tmu_channel *ch = dev_id;
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/* disable or acknowledge interrupt */
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if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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sh_tmu_write(p, TCR, 0x0000);
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if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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sh_tmu_write(ch, TCR, 0x0000);
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else
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sh_tmu_write(p, TCR, 0x0020);
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sh_tmu_write(ch, TCR, 0x0020);
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/* notify clockevent layer */
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p->ced.event_handler(&p->ced);
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ch->ced.event_handler(&ch->ced);
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return IRQ_HANDLED;
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}
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static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
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static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
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{
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return container_of(cs, struct sh_tmu_priv, cs);
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return container_of(cs, struct sh_tmu_channel, cs);
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}
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static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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return sh_tmu_read(p, TCNT) ^ 0xffffffff;
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return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
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}
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static int sh_tmu_clocksource_enable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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int ret;
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if (WARN_ON(p->cs_enabled))
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if (WARN_ON(ch->cs_enabled))
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return 0;
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ret = sh_tmu_enable(p);
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ret = sh_tmu_enable(ch);
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if (!ret) {
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__clocksource_updatefreq_hz(cs, p->rate);
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p->cs_enabled = true;
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__clocksource_updatefreq_hz(cs, ch->rate);
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ch->cs_enabled = true;
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}
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return ret;
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@ -245,45 +256,45 @@ static int sh_tmu_clocksource_enable(struct clocksource *cs)
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static void sh_tmu_clocksource_disable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (WARN_ON(!p->cs_enabled))
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if (WARN_ON(!ch->cs_enabled))
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return;
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sh_tmu_disable(p);
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p->cs_enabled = false;
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sh_tmu_disable(ch);
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ch->cs_enabled = false;
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}
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static void sh_tmu_clocksource_suspend(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (!p->cs_enabled)
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if (!ch->cs_enabled)
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return;
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if (--p->enable_count == 0) {
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__sh_tmu_disable(p);
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pm_genpd_syscore_poweroff(&p->pdev->dev);
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if (--ch->enable_count == 0) {
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__sh_tmu_disable(ch);
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pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
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}
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}
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static void sh_tmu_clocksource_resume(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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if (!p->cs_enabled)
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if (!ch->cs_enabled)
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return;
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if (p->enable_count++ == 0) {
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pm_genpd_syscore_poweron(&p->pdev->dev);
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__sh_tmu_enable(p);
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if (ch->enable_count++ == 0) {
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pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
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__sh_tmu_enable(ch);
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}
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}
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static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
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static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
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char *name, unsigned long rating)
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{
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struct clocksource *cs = &p->cs;
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struct clocksource *cs = &ch->cs;
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cs->name = name;
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cs->rating = rating;
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@ -295,43 +306,43 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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dev_info(&p->pdev->dev, "used as clock source\n");
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dev_info(&ch->tmu->pdev->dev, "used as clock source\n");
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/* Register with dummy 1 Hz value, gets updated in ->enable() */
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clocksource_register_hz(cs, 1);
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return 0;
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}
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static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
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static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_tmu_priv, ced);
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return container_of(ced, struct sh_tmu_channel, ced);
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}
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static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
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static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
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{
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struct clock_event_device *ced = &p->ced;
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struct clock_event_device *ced = &ch->ced;
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sh_tmu_enable(p);
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sh_tmu_enable(ch);
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clockevents_config(ced, p->rate);
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clockevents_config(ced, ch->rate);
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if (periodic) {
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p->periodic = (p->rate + HZ/2) / HZ;
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sh_tmu_set_next(p, p->periodic, 1);
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ch->periodic = (ch->rate + HZ/2) / HZ;
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sh_tmu_set_next(ch, ch->periodic, 1);
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}
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}
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static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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sh_tmu_disable(p);
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sh_tmu_disable(ch);
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disabled = 1;
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break;
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default:
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@ -340,16 +351,18 @@ static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dev_info(&p->pdev->dev, "used for periodic clock events\n");
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sh_tmu_clock_event_start(p, 1);
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dev_info(&ch->tmu->pdev->dev,
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"used for periodic clock events\n");
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sh_tmu_clock_event_start(ch, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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dev_info(&p->pdev->dev, "used for oneshot clock events\n");
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sh_tmu_clock_event_start(p, 0);
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dev_info(&ch->tmu->pdev->dev,
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"used for oneshot clock events\n");
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sh_tmu_clock_event_start(ch, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_tmu_disable(p);
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sh_tmu_disable(ch);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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@ -360,29 +373,29 @@ static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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static int sh_tmu_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
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BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
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/* program new delta value */
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sh_tmu_set_next(p, delta, 0);
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sh_tmu_set_next(ch, delta, 0);
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return 0;
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}
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static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
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pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
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}
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static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
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pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
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}
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static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
|
||||
static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
|
||||
char *name, unsigned long rating)
|
||||
{
|
||||
struct clock_event_device *ced = &p->ced;
|
||||
struct clock_event_device *ced = &ch->ced;
|
||||
int ret;
|
||||
|
||||
memset(ced, 0, sizeof(*ced));
|
||||
|
|
@ -397,27 +410,28 @@ static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
|
|||
ced->suspend = sh_tmu_clock_event_suspend;
|
||||
ced->resume = sh_tmu_clock_event_resume;
|
||||
|
||||
dev_info(&p->pdev->dev, "used for clock events\n");
|
||||
dev_info(&ch->tmu->pdev->dev, "used for clock events\n");
|
||||
|
||||
clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
|
||||
|
||||
ret = request_irq(p->irq, sh_tmu_interrupt,
|
||||
ret = request_irq(ch->irq, sh_tmu_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
|
||||
dev_name(&p->pdev->dev), p);
|
||||
dev_name(&ch->tmu->pdev->dev), ch);
|
||||
if (ret) {
|
||||
dev_err(&p->pdev->dev, "failed to request irq %d\n", p->irq);
|
||||
dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n",
|
||||
ch->irq);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
|
||||
static int sh_tmu_register(struct sh_tmu_channel *ch, char *name,
|
||||
unsigned long clockevent_rating,
|
||||
unsigned long clocksource_rating)
|
||||
{
|
||||
if (clockevent_rating)
|
||||
sh_tmu_register_clockevent(p, name, clockevent_rating);
|
||||
sh_tmu_register_clockevent(ch, name, clockevent_rating);
|
||||
else if (clocksource_rating)
|
||||
sh_tmu_register_clocksource(p, name, clocksource_rating);
|
||||
sh_tmu_register_clocksource(ch, name, clocksource_rating);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -445,8 +459,8 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
|
|||
goto err0;
|
||||
}
|
||||
|
||||
p->irq = platform_get_irq(p->pdev, 0);
|
||||
if (p->irq < 0) {
|
||||
p->channel.irq = platform_get_irq(p->pdev, 0);
|
||||
if (p->channel.irq < 0) {
|
||||
dev_err(&p->pdev->dev, "failed to get irq\n");
|
||||
goto err0;
|
||||
}
|
||||
|
|
@ -470,10 +484,11 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
|
|||
if (ret < 0)
|
||||
goto err2;
|
||||
|
||||
p->cs_enabled = false;
|
||||
p->enable_count = 0;
|
||||
p->channel.cs_enabled = false;
|
||||
p->channel.enable_count = 0;
|
||||
p->channel.tmu = p;
|
||||
|
||||
ret = sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
|
||||
ret = sh_tmu_register(&p->channel, (char *)dev_name(&p->pdev->dev),
|
||||
cfg->clockevent_rating,
|
||||
cfg->clocksource_rating);
|
||||
if (ret < 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue