mirror of https://gitee.com/openkylin/linux.git
ixgbe: Add function ixgbe_reset_pipeline_82599
This patch adds a function that forces a full pipeline reset. This function will be used in following patches to completely reset the PHY during resets. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -2080,6 +2080,50 @@ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
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return ret_val;
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}
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/**
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* ixgbe_reset_pipeline_82599 - perform pipeline reset
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*
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* @hw: pointer to hardware structure
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*
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* Reset pipeline by asserting Restart_AN together with LMS change to ensure
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* full pipeline reset. Note - We must hold the SW/FW semaphore before writing
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* to AUTOC, so this function assumes the semaphore is held.
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**/
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s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
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{
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s32 i, autoc_reg, ret_val;
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s32 anlp1_reg = 0;
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autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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autoc_reg |= IXGBE_AUTOC_AN_RESTART;
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/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
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/* Wait for AN to leave state 0 */
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for (i = 0; i < 10; i++) {
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usleep_range(4000, 8000);
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anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
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if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
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break;
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}
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if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
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hw_dbg(hw, "auto negotiation not completed\n");
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ret_val = IXGBE_ERR_RESET_FAILED;
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goto reset_pipeline_out;
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}
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ret_val = 0;
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reset_pipeline_out:
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/* Write AUTOC register with original LMS field and Restart_AN */
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
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IXGBE_WRITE_FLUSH(hw);
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return ret_val;
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}
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static struct ixgbe_mac_operations mac_ops_82599 = {
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.init_hw = &ixgbe_init_hw_generic,
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.reset_hw = &ixgbe_reset_hw_82599,
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@ -107,6 +107,7 @@ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
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void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
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u32 headroom, int strategy);
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s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
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#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
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#define IXGBE_EMC_INTERNAL_DATA 0x00
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