mirror of https://gitee.com/openkylin/linux.git
sc16is7xx: fix FIFO address of secondary UART
Calls to regmap_raw_read/write needed register rewrite in a similar way as function calls to regmap_read/write already had. This enables reading/writing the serial datastream to the device. Signed-off-by: Bo Svangård <bo.svangard@embeddedart.se> Signed-off-by: Jakub Kicinski <kubakici@wp.pl> Signed-off-by: Jon Ringle <jringle@gridpoint.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -354,6 +354,26 @@ static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
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(reg << SC16IS7XX_REG_SHIFT) | port->line, val);
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}
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static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
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{
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struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
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u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | port->line;
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regcache_cache_bypass(s->regmap, true);
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regmap_raw_read(s->regmap, addr, s->buf, rxlen);
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regcache_cache_bypass(s->regmap, false);
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}
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static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
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{
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struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
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u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | port->line;
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regcache_cache_bypass(s->regmap, true);
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regmap_raw_write(s->regmap, addr, s->buf, to_send);
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regcache_cache_bypass(s->regmap, false);
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}
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static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
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u8 mask, u8 val)
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{
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@ -508,10 +528,7 @@ static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
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s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
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bytes_read = 1;
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} else {
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regcache_cache_bypass(s->regmap, true);
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regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
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s->buf, rxlen);
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regcache_cache_bypass(s->regmap, false);
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sc16is7xx_fifo_read(port, rxlen);
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bytes_read = rxlen;
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}
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@ -591,9 +608,8 @@ static void sc16is7xx_handle_tx(struct uart_port *port)
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s->buf[i] = xmit->buf[xmit->tail];
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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}
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regcache_cache_bypass(s->regmap, true);
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regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
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regcache_cache_bypass(s->regmap, false);
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sc16is7xx_fifo_write(port, to_send);
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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