mirror of https://gitee.com/openkylin/linux.git
drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist
Required for WaEnablePreemptionGranularityControlByUMD:skl,bxt This register is added to HW whitelist to support WA required for future enabling of pre-emptive command execution, WA implementation will be in userspace and it cannot program this register if it is not on HW whitelist. v2: explain purpose of WA (Chris) Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-3-git-send-email-arun.siluvery@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5998,6 +5998,8 @@ enum skl_disp_power_wells {
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#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
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#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
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#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
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/* GEN7 chicken */
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#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
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# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
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@ -910,6 +910,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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int ret;
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/* WaEnableLbsSlaRetryTimerDecrement:skl */
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I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
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@ -980,6 +981,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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/* WaDisableSTUnitPowerOptimization:skl,bxt */
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
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/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
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ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
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if (ret)
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return ret;
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return 0;
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}
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