mirror of https://gitee.com/openkylin/linux.git
arm: Xilinx Zynq SoC patches for v4.2
- Change SoC reset path - Fix SLCR unlock scheme -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlVZ47oACgkQykllyylKDCFw2gCfcaUI+Sy9ewZ5IvbFPa36Kr9e 1JUAn28Ze85ddkUNw/3XxVywSXPre7Ie =eDcD -----END PGP SIGNATURE----- Merge tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx into next/soc Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek: - Change SoC reset path - Fix SLCR unlock scheme * tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart ARM: zynq: Use restart_handler mechanism for slcr reset
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commit
e0f8864fb4
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@ -190,11 +190,6 @@ static void __init zynq_irq_init(void)
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irqchip_init();
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irqchip_init();
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}
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}
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static void zynq_system_reset(enum reboot_mode mode, const char *cmd)
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{
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zynq_slcr_system_reset();
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}
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static const char * const zynq_dt_match[] = {
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static const char * const zynq_dt_match[] = {
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"xlnx,zynq-7000",
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"xlnx,zynq-7000",
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NULL
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NULL
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@ -212,5 +207,4 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
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.init_time = zynq_timer_init,
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.init_time = zynq_timer_init,
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.dt_compat = zynq_dt_match,
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.dt_compat = zynq_dt_match,
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.reserve = zynq_memory_init,
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.reserve = zynq_memory_init,
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.restart = zynq_system_reset,
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MACHINE_END
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MACHINE_END
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@ -21,7 +21,6 @@ void zynq_secondary_startup(void);
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extern int zynq_slcr_init(void);
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extern int zynq_slcr_init(void);
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extern int zynq_early_slcr_init(void);
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extern int zynq_early_slcr_init(void);
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extern void zynq_slcr_system_reset(void);
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extern void zynq_slcr_cpu_stop(int cpu);
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extern void zynq_slcr_cpu_stop(int cpu);
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extern void zynq_slcr_cpu_start(int cpu);
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extern void zynq_slcr_cpu_start(int cpu);
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extern bool zynq_slcr_cpu_state_read(int cpu);
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extern bool zynq_slcr_cpu_state_read(int cpu);
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@ -15,6 +15,7 @@
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*/
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*/
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/reboot.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/regmap.h>
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@ -92,19 +93,20 @@ u32 zynq_slcr_get_device_id(void)
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}
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}
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/**
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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* zynq_slcr_system_restart - Restart the entire system.
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*
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* @nb: Pointer to restart notifier block (unused)
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* @action: Reboot mode (unused)
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* @data: Restart handler private data (unused)
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*
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* Return: 0 always
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*/
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*/
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void zynq_slcr_system_reset(void)
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static
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int zynq_slcr_system_restart(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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{
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u32 reboot;
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u32 reboot;
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/*
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* Unlock the SLCR then reset the system.
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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zynq_slcr_unlock();
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/*
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* the FSBL not loading the bitstream after soft-reboot
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@ -113,8 +115,14 @@ void zynq_slcr_system_reset(void)
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zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
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zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
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return 0;
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}
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}
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static struct notifier_block zynq_slcr_restart_nb = {
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.notifier_call = zynq_slcr_system_restart,
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.priority = 192,
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};
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/**
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/**
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* zynq_slcr_cpu_start - Start cpu
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* zynq_slcr_cpu_start - Start cpu
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* @cpu: cpu number
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* @cpu: cpu number
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@ -219,6 +227,8 @@ int __init zynq_early_slcr_init(void)
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/* unlock the SLCR so that registers can be changed */
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/* unlock the SLCR so that registers can be changed */
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zynq_slcr_unlock();
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zynq_slcr_unlock();
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register_restart_handler(&zynq_slcr_restart_nb);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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of_node_put(np);
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of_node_put(np);
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