mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: apply clocks adjust rules on power state change
This add the apply_clocks_adjust_rules callback which is used to validate the clock settings on a power state change. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
a0a59c8fc7
commit
e17c7f92b2
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@ -1950,6 +1950,166 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
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return size;
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}
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static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
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{
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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struct vega12_single_dpm_table *dpm_table;
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bool vblank_too_short = false;
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bool disable_mclk_switching;
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uint32_t i, latency;
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disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
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!hwmgr->display_config->multi_monitor_in_sync) ||
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vblank_too_short;
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latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
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/* gfxclk */
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dpm_table = &(data->dpm_table.gfx_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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/* memclk */
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dpm_table = &(data->dpm_table.mem_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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/* honour DAL's UCLK Hardmin */
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if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
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dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
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/* Hardmin is dependent on displayconfig */
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if (disable_mclk_switching) {
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
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if (data->mclk_latency_table.entries[i].latency <= latency) {
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if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
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break;
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}
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}
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}
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}
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if (hwmgr->display_config->nb_pstate_switch_disable)
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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/* vclk */
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dpm_table = &(data->dpm_table.vclk_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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/* dclk */
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dpm_table = &(data->dpm_table.dclk_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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/* socclk */
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dpm_table = &(data->dpm_table.soc_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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/* eclk */
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dpm_table = &(data->dpm_table.eclk_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
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if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
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}
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if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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}
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}
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return 0;
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}
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static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
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{
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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@ -2202,6 +2362,8 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
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.display_clock_voltage_request = vega12_display_clock_voltage_request,
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.force_clock_level = vega12_force_clock_level,
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.print_clock_levels = vega12_print_clock_levels,
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.apply_clocks_adjust_rules =
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vega12_apply_clocks_adjust_rules,
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.display_config_changed = vega12_display_configuration_changed_task,
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.powergate_uvd = vega12_power_gate_uvd,
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.powergate_vce = vega12_power_gate_vce,
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@ -443,6 +443,8 @@ struct vega12_hwmgr {
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#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3
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#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3
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#define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2
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#define VEGA12_UMD_PSTATE_UVDCLK_LEVEL 0x3
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#define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL 0x3
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int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
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