Merge branch 'remotes/lorenzo/pci/misc'

- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin
  Kaiser)

- Fix xgene race in installing chained IRQ handler (Martin Kaiser)

- Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar)

- Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas)

* remotes/lorenzo/pci/misc:
  PCI: hv: Fix typo
  PCI: xgene: Fix CRS SV comment
  PCI: brcmstb: Remove chained IRQ handler and data in one go
  PCI: Drop PCIE_RCAR config option
  PCI: xgene-msi: Fix race in installing chained irq handler
  PCI: dwc: Remove IRQ handler and data in one go
  PCI: altera-msi: Remove IRQ handler and data in one go
This commit is contained in:
Bjorn Helgaas 2021-02-24 14:59:25 -06:00
commit e18fb64b79
7 changed files with 15 additions and 31 deletions

View File

@ -55,15 +55,6 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
config PCIE_RCAR
bool "Renesas R-Car PCIe controller"
depends on ARCH_RENESAS || COMPILE_TEST
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_RCAR_HOST
help
Say Y here if you want PCIe controller support on R-Car SoCs.
This option will be removed after arm64 defconfig is updated.
config PCIE_RCAR_HOST
bool "Renesas R-Car PCIe host controller"
depends on ARCH_RENESAS || COMPILE_TEST

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@ -258,10 +258,8 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
static void dw_pcie_free_msi(struct pcie_port *pp)
{
if (pp->msi_irq) {
irq_set_chained_handler(pp->msi_irq, NULL);
irq_set_handler_data(pp->msi_irq, NULL);
}
if (pp->msi_irq)
irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
irq_domain_remove(pp->msi_domain);
irq_domain_remove(pp->irq_domain);

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@ -1714,7 +1714,7 @@ static void prepopulate_bars(struct hv_pcibus_device *hbus)
* resumed and suspended again: see hibernation_snapshot() and
* hibernation_platform_enter().
*
* If the memory enable bit is already set, Hyper-V sliently ignores
* If the memory enable bit is already set, Hyper-V silently ignores
* the below BAR updates, and the related PCI device driver can not
* work, because reading from the device register(s) always returns
* 0xFFFFFFFF.

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@ -384,13 +384,9 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
if (!msi_group->gic_irq)
continue;
irq_set_chained_handler(msi_group->gic_irq,
xgene_msi_isr);
err = irq_set_handler_data(msi_group->gic_irq, msi_group);
if (err) {
pr_err("failed to register GIC IRQ handler\n");
return -EINVAL;
}
irq_set_chained_handler_and_data(msi_group->gic_irq,
xgene_msi_isr, msi_group);
/*
* Statically allocate MSI GIC IRQs to each CPU core.
* With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated

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@ -173,12 +173,13 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
/*
* The v1 controller has a bug in its Configuration Request
* Retry Status (CRS) logic: when CRS is enabled and we read the
* Vendor and Device ID of a non-existent device, the controller
* fabricates return data of 0xFFFF0001 ("device exists but is not
* ready") instead of 0xFFFFFFFF ("device does not exist"). This
* causes the PCI core to retry the read until it times out.
* Avoid this by not claiming to support CRS.
* Retry Status (CRS) logic: when CRS Software Visibility is
* enabled and we read the Vendor and Device ID of a non-existent
* device, the controller fabricates return data of 0xFFFF0001
* ("device exists but is not ready") instead of 0xFFFFFFFF
* ("device does not exist"). This causes the PCI core to retry
* the read until it times out. Avoid this by not claiming to
* support CRS SV.
*/
if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))

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@ -204,8 +204,7 @@ static int altera_msi_remove(struct platform_device *pdev)
struct altera_msi *msi = platform_get_drvdata(pdev);
msi_writel(msi, 0, MSI_INTMASK);
irq_set_chained_handler(msi->irq, NULL);
irq_set_handler_data(msi->irq, NULL);
irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
altera_free_domains(msi);

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@ -614,8 +614,7 @@ static void brcm_msi_remove(struct brcm_pcie *pcie)
if (!msi)
return;
irq_set_chained_handler(msi->irq, NULL);
irq_set_handler_data(msi->irq, NULL);
irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
brcm_free_domains(msi);
}