mirror of https://gitee.com/openkylin/linux.git
arm64: dts: marvell: Add support for Marvell CN9132-DB
Extend the support of the CN9131 with yet another additional CP115. The last number indicates how many external CP115 are used. New available interfaces: * CP2 CRYPTO-0 (disabled) * CP2 ETH-0 (SFI, problem with the SFP cage, disabled) * CP2 GPIO-1 * CP2 GPIO-2 * CP2 I2C-0 * CP2 PCIe-0 x2 * CP2 PCIe-2 x1 (disabled) * CP2 SDHCI-0 * CP2 USB3-1 (High-speed) Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Grzegorz Jaszczyk
Gregory CLEMENT
parent
fe5e610f16
commit
e1bd6ca9f8
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@ -12,3 +12,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
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@ -0,0 +1,221 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9132-DB board.
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*/
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#include "cn9131-db.dts"
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/ {
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model = "Marvell Armada CN9132-DB";
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compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
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"marvell,armada-ap807-quad", "marvell,armada-ap807";
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aliases {
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gpio5 = &cp2_gpio1;
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gpio6 = &cp2_gpio2;
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ethernet5 = &cp2_eth0;
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};
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cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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cp2_usb3_0_phy0: cp2_usb3_phy0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp2_reg_usb3_vbus0>;
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};
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cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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cp2_usb3_0_phy1: cp2_usb3_phy1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp2_reg_usb3_vbus1>;
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};
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cp2_reg_sd_vccq: cp2_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp2_sd_vcc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1 3300000 0x0>;
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};
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cp2_sfp_eth0: sfp-eth0 {
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compatible = "sff,sfp";
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i2c-bus = <&cp2_sfpp0_i2c>;
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los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
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/*
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* SFP cages are unconnected on early PCBs because of an the I2C
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* lanes not being connected. Prevent the port for being
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* unusable by disabling the SFP node.
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*/
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status = "disabled";
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};
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};
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/*
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* Instantiate the second slave CP115
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*/
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#define CP11X_NAME cp2
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#define CP11X_BASE f6000000
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#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f6600000
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#define CP11X_PCIE1_BASE f6620000
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#define CP11X_PCIE2_BASE f6640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp2_crypto {
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status = "disabled";
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};
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&cp2_ethernet {
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status = "okay";
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};
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/* SLM-1521-V2, CON9 */
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&cp2_eth0 {
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status = "disabled";
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phy-mode = "10gbase-kr";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp2_comphy4 0>;
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managed = "in-band-status";
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sfp = <&cp2_sfp_eth0>;
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};
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&cp2_gpio1 {
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status = "okay";
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};
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&cp2_gpio2 {
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status = "okay";
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};
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&cp2_i2c0 {
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clock-frequency = <100000>;
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/* SLM-1521-V2 - U3 */
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i2c-mux@72 {
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72>;
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cp2_sfpp0_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* U12 */
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cp2_module_expander1: pca9555@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x21>;
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};
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};
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};
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};
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/* SLM-1521-V2, CON6 */
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&cp2_pcie0 {
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status = "okay";
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num-lanes = <2>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp2_comphy0 0
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&cp2_comphy1 0>;
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};
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/* SLM-1521-V2, CON8 */
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&cp2_pcie2 {
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status = "okay";
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num-lanes = <1>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp2_comphy5 2>;
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};
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&cp2_sata0 {
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status = "okay";
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/* SLM-1521-V2, CON4 */
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sata-port@0 {
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/* Generic PHY, providing serdes lanes */
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phys = <&cp2_comphy2 0>;
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};
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};
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/* CON 2 on SLM-1683 - microSD */
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&cp2_sdhci0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_sdhci_pins>;
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bus-width = <4>;
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cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
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vqmmc-supply = <&cp2_reg_sd_vccq>;
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};
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&cp2_syscon0 {
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cp2_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp2_i2c0_pins: cp2-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp2_sdhci_pins: cp2-sdhi-pins-0 {
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marvell,pins = "mpp56", "mpp57", "mpp58",
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"mpp59", "mpp60", "mpp61";
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marvell,function = "sdio";
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};
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};
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};
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&cp2_usb3_0 {
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status = "okay";
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usb-phy = <&cp2_usb3_0_phy0>;
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phy-names = "usb";
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};
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/* SLM-1521-V2, CON11 */
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&cp2_usb3_1 {
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status = "okay";
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usb-phy = <&cp2_usb3_0_phy1>;
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phy-names = "usb";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp2_comphy3 1>;
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};
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