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ARM: imx53: qsrb: fix PMIC interrupt level 

The MC34708 PMIC interrupt level is active high, but was set to
active low in the devicetree, probably as a result of a copy and
paste error from the QSB board.

This caused IRQ storms and led to the kernel disabling the PMIC
interrupt.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Lucas Stach 2015-08-19 15:19:47 +02:00 committed by Shawn Guo
parent 34adba7117
commit e1ffceb078
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/imx53-qsrb.dts
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@ -36,7 +36,7 @@ pmic: mc34708@8 {
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <23 0x8>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
regulators {
sw1_reg: sw1a {
regulator-name = "SW1";