mirror of https://gitee.com/openkylin/linux.git
staging: mt7621-pci: avoid use of global variable 'pcie_link_status'
'pcie_link_status' is a global variable which is being used as a mask to know which virtual bridges are or not enabled. Instead of this extract a new 'mt7621_pcie_init_virtual_bridges' function where a similar local variable is used for the same task. This allow us to properly configure the virtual PCI-PCI bridges in configuration registers of the mt7621 pci controller. For a correct initiation of which is connected use 'enabled' field of 'mt7621_pcie_port' struct. With this change driver probe function gets a bit cleaner and readable. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos
Greg Kroah-Hartman
parent
a41a1f8618
commit
e2200279af
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@ -64,6 +64,14 @@
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#define MT7621_PCIE_OFFSET 0x2000
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#define MT7621_NEXT_PORT 0x1000
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#define MT7621_BR0_MASK GENMASK(19, 16)
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#define MT7621_BR1_MASK GENMASK(23, 20)
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#define MT7621_BR2_MASK GENMASK(27, 24)
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#define MT7621_BR_ALL_MASK GENMASK(27, 16)
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#define MT7621_BR0_SHIFT 16
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#define MT7621_BR1_SHIFT 20
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#define MT7621_BR2_SHIFT 24
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#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
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#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
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#define RALINK_PCI_ID 0x0030
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@ -82,8 +90,6 @@
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#define MEMORY_BASE 0x0
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static int pcie_link_status;
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/* pcie phy related macros */
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
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#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
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@ -589,10 +595,8 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
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reset_control_assert(port->pcie_rst);
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rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
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pcie_link_status &= ~(1 << slot);
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port->enabled = false;
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} else {
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pcie_link_status |= BIT(slot);
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port->enabled = true;
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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/* enable pcie interrupt */
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@ -643,6 +647,70 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
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}
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}
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static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
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{
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u32 pcie_link_status = 0;
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u32 val= 0;
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struct mt7621_pcie_port *port;
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list_for_each_entry(port, &pcie->ports, list) {
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u32 slot = port->slot;
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if (port->enabled)
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pcie_link_status |= BIT(slot);
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}
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if (pcie_link_status == 0)
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return -1;
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/*
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* pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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* 3'b000 x x x
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* 3'b001 x x 0
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* 3'b010 x 0 x
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* 3'b011 x 1 0
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* 3'b100 0 x x
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* 3'b101 1 x 0
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* 3'b110 1 0 x
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* 3'b111 2 1 0
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*/
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switch (pcie_link_status) {
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case 2:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
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val |= 0x1 << MT7621_BR0_SHIFT;
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val |= 0x0 << MT7621_BR1_SHIFT;
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 4:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~MT7621_BR_ALL_MASK;
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val |= 0x1 << MT7621_BR0_SHIFT;
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val |= 0x2 << MT7621_BR1_SHIFT;
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val |= 0x0 << MT7621_BR2_SHIFT;
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 5:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~MT7621_BR_ALL_MASK;
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val |= 0x0 << MT7621_BR0_SHIFT;
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val |= 0x2 << MT7621_BR1_SHIFT;
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val |= 0x1 << MT7621_BR2_SHIFT;
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 6:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~MT7621_BR_ALL_MASK;
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val |= 0x2 << MT7621_BR0_SHIFT;
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val |= 0x0 << MT7621_BR1_SHIFT;
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val |= 0x1 << MT7621_BR2_SHIFT;
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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}
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return 0;
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}
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static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
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struct list_head *res)
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{
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@ -693,7 +761,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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struct pci_host_bridge *bridge;
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struct mt7621_pcie_port *port, *tmp;
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int err;
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u32 val = 0;
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LIST_HEAD(res);
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if (!dev->of_node)
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@ -751,52 +818,10 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7); // set DATA
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mdelay(1000);
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if (pcie_link_status == 0)
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err = mt7621_pcie_init_virtual_bridges(pcie);
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if (err) {
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dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
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return 0;
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/*
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pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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3'b000 x x x
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3'b001 x x 0
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3'b010 x 0 x
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3'b011 x 1 0
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3'b100 0 x x
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3'b101 1 x 0
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3'b110 1 0 x
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3'b111 2 1 0
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*/
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switch (pcie_link_status) {
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case 2:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~0x00ff0000;
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val |= 0x1 << 16; // port 0
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val |= 0x0 << 20; // port 1
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 4:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~0x0fff0000;
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val |= 0x1 << 16; //port0
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val |= 0x2 << 20; //port1
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val |= 0x0 << 24; //port2
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 5:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~0x0fff0000;
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val |= 0x0 << 16; //port0
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val |= 0x2 << 20; //port1
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val |= 0x1 << 24; //port2
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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case 6:
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~0x0fff0000;
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val |= 0x2 << 16; //port0
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val |= 0x0 << 20; //port1
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val |= 0x1 << 24; //port2
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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break;
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}
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pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
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