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ARM: dts: r7s9210: Add IRQC device node 

Enable support for the IRQC on RZ/A2M, which is a small front-end to the
GIC.  This allows to use up to 8 external interrupts with configurable
sense select.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Chris Brandt 2019-06-04 15:09:13 -05:00 committed by Simon Horman
parent 1de78ccbda
commit e23391f36c
1 changed files with 19 additions and 0 deletions
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19
arch/arm/boot/dts/r7s9210.dtsi
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@ -473,6 +473,25 @@ bsid: chipid@fcfe8004 {
reg = <0xfcfe8004 4>; reg = <0xfcfe8004 4>;
}; };
irqc: interrupt-controller@fcfef800 {
compatible = "renesas,r7s9210-irqc",
"renesas,rza1-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xfcfef800 0x6>;
interrupt-map =
<0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <7 0>;
};
pinctrl: pin-controller@fcffe000 { pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl"; compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>; reg = <0xfcffe000 0x1000>;