mirror of https://gitee.com/openkylin/linux.git
drm/i915: ring irq cleanups
- gen6 put/get only need one argument rflags and gflags are always the same (see above explanation) - remove a couple redundantly defined IRQs - reordered some lines to make things go in descending order Every ring has its own interrupts, enables, masks, and status bits that are fed into the main interrupt enable/mask/status registers. At one point in time it seemed like a good idea to make our functions support the notion that each interrupt may have a different bit position in the corresponding register (blitter parser error may be bit n in IMR, but bit m in blitter IMR). It turned out though that the HW designers did us a solid on Gen6+ and this unfortunate situation has been avoided. This allows our interrupt code to be cleaned up a bit. I jammed this into one commit because there should be no functional change with this commit, and staging it into multiple commits was unnecessarily artificial IMO. CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: - fixed up merged conflict with vlv changes. - added GEN6 to GT blitter bit, we only use it on gen6+. - added a comment to both ring irq bits and GT irq bits that on gen6+ these alias. - added comment that GT_BSD_USER_INTERRUPT is ilk-only. - I've got confused a bit that we still use GT_USER_INTERRUPT on ivb for the render ring - but this goes back to ilk where we have only gt interrupt bits and so we be equally confusing if changed.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -462,7 +462,7 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[VCS]);
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if (gt_iir & GT_BLT_USER_INTERRUPT)
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if (gt_iir & GT_GEN6_BLT_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[BCS]);
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if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
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@ -620,9 +620,9 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
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if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
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if (gt_iir & GEN6_BSD_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[VCS]);
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if (gt_iir & GT_BLT_USER_INTERRUPT)
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if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[BCS]);
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if (de_iir & DE_GSE_IVB)
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@ -688,7 +688,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
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atomic_inc(&dev_priv->irq_received);
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if (IS_GEN6(dev))
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bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
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bsd_usr_interrupt = GEN6_BSD_USER_INTERRUPT;
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/* disable master interrupt before clearing iir */
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de_ier = I915_READ(DEIER);
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@ -722,7 +722,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (gt_iir & bsd_usr_interrupt)
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notify_ring(dev, &dev_priv->ring[VCS]);
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if (gt_iir & GT_BLT_USER_INTERRUPT)
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if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[BCS]);
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if (de_iir & DE_GSE)
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@ -2081,8 +2081,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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if (IS_GEN6(dev))
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render_irqs =
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GT_USER_INTERRUPT |
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GT_GEN6_BSD_USER_INTERRUPT |
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GT_BLT_USER_INTERRUPT;
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GEN6_BSD_USER_INTERRUPT |
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GEN6_BLITTER_USER_INTERRUPT;
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else
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render_irqs =
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GT_USER_INTERRUPT |
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@ -2154,8 +2154,8 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
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GT_BLT_USER_INTERRUPT;
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render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
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GEN6_BLITTER_USER_INTERRUPT;
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I915_WRITE(GTIER, render_irqs);
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POSTING_READ(GTIER);
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@ -2218,7 +2218,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
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render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
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GT_GEN6_BLT_CS_ERROR_INTERRUPT |
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GT_BLT_USER_INTERRUPT |
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GT_GEN6_BLT_USER_INTERRUPT |
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GT_GEN6_BSD_USER_INTERRUPT |
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GT_GEN6_BSD_CS_ERROR_INTERRUPT |
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GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
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@ -643,7 +643,9 @@
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#define CACHE_MODE_1 0x7004 /* IVB+ */
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#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
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/* GEN6 interrupt control */
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/* GEN6 interrupt control
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* Note that the per-ring interrupt bits do alias with the global interrupt bits
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* in GTIMR. */
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#define GEN6_RENDER_HWSTAM 0x2098
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#define GEN6_RENDER_IMR 0x20a8
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#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
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@ -3203,13 +3205,15 @@
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#define DEIIR 0x44008
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#define DEIER 0x4400c
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/* GT interrupt */
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/* GT interrupt.
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* Note that for gen6+ the ring-specific interrupt bits do alias with the
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* corresponding bits in the per-ring interrupt control registers. */
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#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
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#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
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#define GT_BLT_USER_INTERRUPT (1 << 22)
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#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
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#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
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#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
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#define GT_BSD_USER_INTERRUPT (1 << 5)
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#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
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#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
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#define GT_PIPE_NOTIFY (1 << 4)
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#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
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@ -788,7 +788,7 @@ ring_add_request(struct intel_ring_buffer *ring,
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}
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static bool
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gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 mask)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -803,9 +803,9 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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spin_lock(&ring->irq_lock);
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if (ring->irq_refcount++ == 0) {
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ring->irq_mask &= ~rflag;
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ring->irq_mask &= ~mask;
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I915_WRITE_IMR(ring, ring->irq_mask);
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ironlake_enable_irq(dev_priv, gflag);
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ironlake_enable_irq(dev_priv, mask);
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}
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spin_unlock(&ring->irq_lock);
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@ -813,16 +813,16 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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}
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static void
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gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 mask)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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spin_lock(&ring->irq_lock);
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if (--ring->irq_refcount == 0) {
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ring->irq_mask |= rflag;
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ring->irq_mask |= mask;
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I915_WRITE_IMR(ring, ring->irq_mask);
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ironlake_disable_irq(dev_priv, gflag);
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ironlake_disable_irq(dev_priv, mask);
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}
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spin_unlock(&ring->irq_lock);
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@ -1376,33 +1376,25 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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static bool
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gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_get_irq(ring,
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GT_USER_INTERRUPT,
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GEN6_RENDER_USER_INTERRUPT);
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return gen6_ring_get_irq(ring, GT_USER_INTERRUPT);
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}
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static void
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gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_put_irq(ring,
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GT_USER_INTERRUPT,
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GEN6_RENDER_USER_INTERRUPT);
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return gen6_ring_put_irq(ring, GT_USER_INTERRUPT);
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}
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static bool
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gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_get_irq(ring,
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GT_GEN6_BSD_USER_INTERRUPT,
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GEN6_BSD_USER_INTERRUPT);
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return gen6_ring_get_irq(ring, GEN6_BSD_USER_INTERRUPT);
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}
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static void
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gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_put_irq(ring,
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GT_GEN6_BSD_USER_INTERRUPT,
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GEN6_BSD_USER_INTERRUPT);
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return gen6_ring_put_irq(ring, GEN6_BSD_USER_INTERRUPT);
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}
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/* ring buffer for Video Codec for Gen6+ */
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@ -1431,17 +1423,13 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
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static bool
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blt_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_get_irq(ring,
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GT_BLT_USER_INTERRUPT,
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GEN6_BLITTER_USER_INTERRUPT);
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return gen6_ring_get_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
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}
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static void
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blt_ring_put_irq(struct intel_ring_buffer *ring)
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{
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gen6_ring_put_irq(ring,
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GT_BLT_USER_INTERRUPT,
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GEN6_BLITTER_USER_INTERRUPT);
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gen6_ring_put_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
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}
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static int blt_ring_flush(struct intel_ring_buffer *ring,
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