mirror of https://gitee.com/openkylin/linux.git
sky2: add Wake On Lan support
Adds basic magic packet wake on lan support to the sky2 driver. Note: initial WOL value is based on BIOS settings. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
dde6d43d06
commit
e3173832d7
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@ -567,6 +567,73 @@ static void sky2_phy_reinit(struct sky2_port *sky2)
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spin_unlock_bh(&sky2->phy_lock);
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}
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/* Put device in state to listen for Wake On Lan */
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static void sky2_wol_init(struct sky2_port *sky2)
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{
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struct sky2_hw *hw = sky2->hw;
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unsigned port = sky2->port;
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enum flow_control save_mode;
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u16 ctrl;
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u32 reg1;
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/* Bring hardware out of reset */
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sky2_write16(hw, B0_CTST, CS_RST_CLR);
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sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
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sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
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sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
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/* Force to 10/100
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* sky2_reset will re-enable on resume
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*/
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save_mode = sky2->flow_mode;
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ctrl = sky2->advertising;
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sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
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sky2->flow_mode = FC_NONE;
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sky2_phy_power(hw, port, 1);
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sky2_phy_reinit(sky2);
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sky2->flow_mode = save_mode;
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sky2->advertising = ctrl;
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/* Set GMAC to no flow control and auto update for speed/duplex */
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gma_write16(hw, port, GM_GP_CTRL,
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GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
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GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
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/* Set WOL address */
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memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
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sky2->netdev->dev_addr, ETH_ALEN);
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/* Turn on appropriate WOL control bits */
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sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
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ctrl = 0;
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if (sky2->wol & WAKE_PHY)
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ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
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else
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ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
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if (sky2->wol & WAKE_MAGIC)
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ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
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else
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ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
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ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
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sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
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/* Turn on legacy PCI-Express PME mode */
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
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reg1 |= PCI_Y2_PME_LEGACY;
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sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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/* block receiver */
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sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
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}
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static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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{
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struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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@ -2404,11 +2471,9 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
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}
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static int sky2_reset(struct sky2_hw *hw)
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static int __devinit sky2_init(struct sky2_hw *hw)
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{
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u16 status;
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u8 t8;
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int i;
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sky2_write8(hw, B0_CTST, CS_RST_CLR);
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@ -2429,6 +2494,22 @@ static int sky2_reset(struct sky2_hw *hw)
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return -EOPNOTSUPP;
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}
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hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
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hw->ports = 1;
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t8 = sky2_read8(hw, B2_Y2_HW_RES);
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if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
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if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
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++hw->ports;
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}
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return 0;
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}
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static void sky2_reset(struct sky2_hw *hw)
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{
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u16 status;
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int i;
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/* disable ASF */
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if (hw->chip_id <= CHIP_ID_YUKON_EC) {
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
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@ -2453,14 +2534,6 @@ static int sky2_reset(struct sky2_hw *hw)
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sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
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hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
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hw->ports = 1;
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t8 = sky2_read8(hw, B2_Y2_HW_RES);
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if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
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if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
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++hw->ports;
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}
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sky2_power_on(hw);
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for (i = 0; i < hw->ports; i++) {
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@ -2544,7 +2617,37 @@ static int sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
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sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
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sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
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}
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static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
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{
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return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
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}
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static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
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const struct sky2_port *sky2 = netdev_priv(dev);
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wol->supported = sky2_wol_supported(sky2->hw);
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wol->wolopts = sky2->wol;
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}
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static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
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struct sky2_port *sky2 = netdev_priv(dev);
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struct sky2_hw *hw = sky2->hw;
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if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
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return -EOPNOTSUPP;
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sky2->wol = wol->wolopts;
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if (hw->chip_id == CHIP_ID_YUKON_EC_U)
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sky2_write32(hw, B0_CTST, sky2->wol
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? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
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if (!netif_running(dev))
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sky2_wol_init(sky2);
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return 0;
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}
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@ -3156,7 +3259,9 @@ static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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static const struct ethtool_ops sky2_ethtool_ops = {
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.get_settings = sky2_get_settings,
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.set_settings = sky2_set_settings,
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.get_drvinfo = sky2_get_drvinfo,
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.get_drvinfo = sky2_get_drvinfo,
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.get_wol = sky2_get_wol,
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.set_wol = sky2_set_wol,
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.get_msglevel = sky2_get_msglevel,
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.set_msglevel = sky2_set_msglevel,
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.nway_reset = sky2_nway_reset,
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@ -3186,7 +3291,8 @@ static const struct ethtool_ops sky2_ethtool_ops = {
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/* Initialize network device */
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static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
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unsigned port, int highmem)
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unsigned port,
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int highmem, int wol)
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{
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struct sky2_port *sky2;
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struct net_device *dev = alloc_etherdev(sizeof(*sky2));
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@ -3234,6 +3340,7 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
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sky2->speed = -1;
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sky2->advertising = sky2_supported_modes(hw);
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sky2->rx_csum = 1;
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sky2->wol = wol;
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spin_lock_init(&sky2->phy_lock);
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sky2->tx_pending = TX_DEF_PENDING;
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@ -3336,12 +3443,24 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
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return err;
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}
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static int __devinit pci_wake_enabled(struct pci_dev *dev)
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{
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int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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u16 value;
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if (!pm)
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return 0;
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if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
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return 0;
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return value & PCI_PM_CTRL_PME_ENABLE;
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}
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static int __devinit sky2_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct net_device *dev;
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struct sky2_hw *hw;
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int err, using_dac = 0;
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int err, using_dac = 0, wol_default;
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err = pci_enable_device(pdev);
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if (err) {
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@ -3378,6 +3497,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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}
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}
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wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
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err = -ENOMEM;
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hw = kzalloc(sizeof(*hw), GFP_KERNEL);
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if (!hw) {
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@ -3413,7 +3534,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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if (!hw->st_le)
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goto err_out_iounmap;
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err = sky2_reset(hw);
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err = sky2_init(hw);
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if (err)
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goto err_out_iounmap;
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@ -3422,7 +3543,9 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
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hw->chip_id, hw->chip_rev);
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dev = sky2_init_netdev(hw, 0, using_dac);
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sky2_reset(hw);
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dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
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if (!dev) {
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err = -ENOMEM;
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goto err_out_free_pci;
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@ -3457,7 +3580,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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if (hw->ports > 1) {
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struct net_device *dev1;
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dev1 = sky2_init_netdev(hw, 1, using_dac);
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dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
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if (!dev1) {
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printk(KERN_WARNING PFX
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"allocation of second port failed\n");
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@ -3544,23 +3667,29 @@ static void __devexit sky2_remove(struct pci_dev *pdev)
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static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct sky2_hw *hw = pci_get_drvdata(pdev);
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int i;
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int i, wol = 0;
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del_timer_sync(&hw->idle_timer);
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netif_poll_disable(hw->dev[0]);
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for (i = 0; i < hw->ports; i++) {
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struct net_device *dev = hw->dev[i];
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struct sky2_port *sky2 = netdev_priv(dev);
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if (netif_running(dev)) {
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if (netif_running(dev))
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sky2_down(dev);
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netif_device_detach(dev);
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}
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if (sky2->wol)
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sky2_wol_init(sky2);
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wol |= sky2->wol;
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}
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sky2_write32(hw, B0_IMSK, 0);
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sky2_power_aux(hw);
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pci_save_state(pdev);
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pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
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pci_set_power_state(pdev, pci_choose_state(pdev, state));
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return 0;
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@ -3580,18 +3709,13 @@ static int sky2_resume(struct pci_dev *pdev)
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goto out;
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pci_enable_wake(pdev, PCI_D0, 0);
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err = sky2_reset(hw);
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if (err)
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goto out;
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sky2_reset(hw);
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sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
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for (i = 0; i < hw->ports; i++) {
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struct net_device *dev = hw->dev[i];
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if (netif_running(dev)) {
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netif_device_attach(dev);
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err = sky2_up(dev);
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if (err) {
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printk(KERN_ERR PFX "%s: could not up: %d\n",
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@ -3612,6 +3736,35 @@ static int sky2_resume(struct pci_dev *pdev)
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}
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#endif
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static void sky2_shutdown(struct pci_dev *pdev)
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{
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struct sky2_hw *hw = pci_get_drvdata(pdev);
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int i, wol = 0;
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del_timer_sync(&hw->idle_timer);
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netif_poll_disable(hw->dev[0]);
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for (i = 0; i < hw->ports; i++) {
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struct net_device *dev = hw->dev[i];
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struct sky2_port *sky2 = netdev_priv(dev);
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if (sky2->wol) {
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wol = 1;
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sky2_wol_init(sky2);
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}
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}
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if (wol)
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sky2_power_aux(hw);
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pci_enable_wake(pdev, PCI_D3hot, wol);
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pci_enable_wake(pdev, PCI_D3cold, wol);
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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}
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static struct pci_driver sky2_driver = {
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.name = DRV_NAME,
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.id_table = sky2_id_table,
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@ -3621,6 +3774,7 @@ static struct pci_driver sky2_driver = {
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.suspend = sky2_suspend,
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.resume = sky2_resume,
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#endif
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.shutdown = sky2_shutdown,
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};
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static int __init sky2_init_module(void)
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@ -32,6 +32,7 @@ enum pci_dev_reg_1 {
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PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
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PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
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PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
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PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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};
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enum pci_dev_reg_2 {
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@ -837,33 +838,27 @@ enum {
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GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
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/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
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WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
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WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
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WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
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WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
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WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
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WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
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WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
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WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
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/* WOL Pattern Length Registers (YUKON only) */
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WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
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WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
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/* WOL Pattern Counter Registers (YUKON only) */
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WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
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WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
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};
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#define WOL_REGS(port, x) (x + (port)*0x80)
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enum {
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WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
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WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
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};
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#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
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enum {
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BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
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@ -1715,14 +1710,17 @@ enum {
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GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
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#define GMAC_DEF_MSK GM_IS_TX_FF_UR
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};
|
||||
|
||||
/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
|
||||
/* Bits 15.. 2: reserved */
|
||||
enum { /* Bits 15.. 2: reserved */
|
||||
GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
|
||||
GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
|
||||
};
|
||||
|
||||
|
||||
/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
|
||||
enum {
|
||||
WOL_CTL_LINK_CHG_OCC = 1<<15,
|
||||
WOL_CTL_MAGIC_PKT_OCC = 1<<14,
|
||||
WOL_CTL_PATTERN_OCC = 1<<13,
|
||||
|
|
@ -1741,17 +1739,6 @@ enum {
|
|||
WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
|
||||
};
|
||||
|
||||
#define WOL_CTL_DEFAULT \
|
||||
(WOL_CTL_DIS_PME_ON_LINK_CHG | \
|
||||
WOL_CTL_DIS_PME_ON_PATTERN | \
|
||||
WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
|
||||
WOL_CTL_DIS_LINK_CHG_UNIT | \
|
||||
WOL_CTL_DIS_PATTERN_UNIT | \
|
||||
WOL_CTL_DIS_MAGIC_PKT_UNIT)
|
||||
|
||||
/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
|
||||
#define WOL_CTL_PATT_ENA(x) (1 << (x))
|
||||
|
||||
|
||||
/* Control flags */
|
||||
enum {
|
||||
|
|
@ -1875,6 +1862,7 @@ struct sky2_port {
|
|||
u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
|
||||
u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
|
||||
u8 rx_csum;
|
||||
u8 wol;
|
||||
enum flow_control flow_mode;
|
||||
enum flow_control flow_status;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue