mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: add sys interface to set pp_od_clk_voltage for smu
Add sys interface to set pp_od_clk_voltage for smu. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
Alex Deucher
parent
e9c5b46e3c
commit
e388cc474d
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@ -649,19 +649,29 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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tmp_str++;
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}
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if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
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ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
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if (is_support_sw_smu(adev)) {
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ret = smu_od_edit_dpm_table(&adev->smu, type,
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parameter, parameter_size);
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if (ret)
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return -EINVAL;
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} else {
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if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
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ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
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parameter, parameter_size);
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if (ret)
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return -EINVAL;
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if (type == PP_OD_COMMIT_DPM_TABLE) {
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if (adev->powerplay.pp_funcs->dispatch_tasks) {
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amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
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return count;
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} else {
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if (ret)
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return -EINVAL;
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if (type == PP_OD_COMMIT_DPM_TABLE) {
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if (adev->powerplay.pp_funcs->dispatch_tasks) {
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amdgpu_dpm_dispatch_task(adev,
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AMD_PP_TASK_READJUST_POWER_STATE,
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NULL);
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return count;
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} else {
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return -EINVAL;
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}
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}
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}
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@ -310,6 +310,8 @@ struct smu_table_context
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uint32_t *od_settings_min;
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void *overdrive_table;
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void *od8_settings;
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bool od_gfxclk_update;
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bool od_memclk_update;
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};
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struct smu_dpm_context {
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@ -417,6 +419,9 @@ struct pptable_funcs {
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int (*set_od_percentage)(struct smu_context *smu,
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enum pp_clock_type type,
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uint32_t value);
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int (*od_edit_dpm_table)(struct smu_context *smu,
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enum PP_OD_DPM_TABLE_COMMAND type,
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long *input, uint32_t size);
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int (*get_clock_by_type_with_latency)(struct smu_context *smu,
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enum amd_pp_clock_type type,
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struct
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@ -603,6 +608,8 @@ struct smu_funcs
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((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
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#define smu_set_od_percentage(smu, type, value) \
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((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
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#define smu_od_edit_dpm_table(smu, type, input, size) \
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((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
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#define smu_start_thermal_control(smu) \
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((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
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#define smu_read_sensor(smu, sensor, data, size) \
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@ -1985,6 +1985,228 @@ static int vega20_set_od_percentage(struct smu_context *smu,
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return 0;
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}
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static int vega20_odn_edit_dpm_table(struct smu_context *smu,
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enum PP_OD_DPM_TABLE_COMMAND type,
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long *input, uint32_t size)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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OverDriveTable_t *od_table =
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(OverDriveTable_t *)(table_context->overdrive_table);
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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struct vega20_dpm_table *dpm_table = NULL;
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struct vega20_single_dpm_table *single_dpm_table;
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struct vega20_od8_settings *od8_settings =
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(struct vega20_od8_settings *)table_context->od8_settings;
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struct pp_clock_levels_with_latency clocks;
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int32_t input_index, input_clk, input_vol, i;
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int od8_id, ret;
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dpm_table = smu_dpm->dpm_context;
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if (!input) {
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pr_warn("NULL user input for clock and voltage\n");
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return -EINVAL;
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}
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switch (type) {
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case PP_OD_EDIT_SCLK_VDDC_TABLE:
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if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
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pr_info("Sclk min/max frequency overdrive not supported\n");
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return -EOPNOTSUPP;
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}
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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pr_info("invalid number of input parameters %d\n", size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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if (input_index != 0 && input_index != 1) {
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pr_info("Invalid index %d\n", input_index);
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pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
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return -EINVAL;
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}
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if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
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input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
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return -EINVAL;
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}
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if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
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od_table->GfxclkFmin = input_clk;
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table_context->od_gfxclk_update = true;
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} else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
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od_table->GfxclkFmax = input_clk;
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table_context->od_gfxclk_update = true;
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}
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}
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break;
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case PP_OD_EDIT_MCLK_VDDC_TABLE:
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if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
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pr_info("Mclk max frequency overdrive not supported\n");
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return -EOPNOTSUPP;
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}
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single_dpm_table = &(dpm_table->mem_table);
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ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
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if (ret) {
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pr_err("Attempt to get memory clk levels Failed!");
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return ret;
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}
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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pr_info("invalid number of input parameters %d\n",
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size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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if (input_index != 1) {
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pr_info("Invalid index %d\n", input_index);
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pr_info("Support max Mclk frequency setting only which index by 1\n");
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return -EINVAL;
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}
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if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
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input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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clocks.data[0].clocks_in_khz / 1000,
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od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
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return -EINVAL;
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}
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if (input_index == 1 && od_table->UclkFmax != input_clk) {
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table_context->od_gfxclk_update = true;
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od_table->UclkFmax = input_clk;
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}
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}
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break;
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case PP_OD_EDIT_VDDC_CURVE:
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if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
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pr_info("Voltage curve calibrate not supported\n");
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return -EOPNOTSUPP;
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}
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for (i = 0; i < size; i += 3) {
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if (i + 3 > size) {
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pr_info("invalid number of input parameters %d\n",
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size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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input_vol = input[i + 2];
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if (input_index > 2) {
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pr_info("Setting for point %d is not supported\n",
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input_index + 1);
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pr_info("Three supported points index by 0, 1, 2\n");
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return -EINVAL;
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}
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od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
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if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
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input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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od8_settings->od8_settings_array[od8_id].min_value,
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od8_settings->od8_settings_array[od8_id].max_value);
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return -EINVAL;
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}
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od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
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if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
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input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
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pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
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input_vol,
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od8_settings->od8_settings_array[od8_id].min_value,
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od8_settings->od8_settings_array[od8_id].max_value);
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return -EINVAL;
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}
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switch (input_index) {
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case 0:
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od_table->GfxclkFreq1 = input_clk;
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od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
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break;
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case 1:
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od_table->GfxclkFreq2 = input_clk;
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od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
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break;
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case 2:
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od_table->GfxclkFreq3 = input_clk;
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od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
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break;
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}
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}
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break;
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case PP_OD_RESTORE_DEFAULT_TABLE:
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ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
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if (ret) {
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pr_err("Failed to export over drive table!\n");
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return ret;
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}
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break;
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case PP_OD_COMMIT_DPM_TABLE:
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ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
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if (ret) {
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pr_err("Failed to import over drive table!\n");
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return ret;
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}
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/* retrieve updated gfxclk table */
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if (table_context->od_gfxclk_update) {
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table_context->od_gfxclk_update = false;
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single_dpm_table = &(dpm_table->gfx_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_GFXCLK);
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if (ret) {
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pr_err("[Setoverdrive] failed to refresh dpm table!\n");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
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}
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct pptable_funcs vega20_ppt_funcs = {
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.alloc_dpm_context = vega20_allocate_dpm_context,
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.store_powerplay_table = vega20_store_powerplay_table,
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@ -2006,6 +2228,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
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.force_performance_level = vega20_force_performance_level,
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.update_specified_od8_value = vega20_update_specified_od8_value,
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.set_od_percentage = vega20_set_od_percentage,
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.od_edit_dpm_table = vega20_odn_edit_dpm_table,
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};
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void vega20_set_ppt_funcs(struct smu_context *smu)
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