mirror of https://gitee.com/openkylin/linux.git
[IA64] Remove block structure for locking in iosapic.c
Remove unnecessary indent between spin_lock() and spin_unlock() in iosapic.c. This has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Yasuaki Ishimatsu
Tony Luck
parent
a5fcaa2106
commit
e3a8f7b8b6
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@ -209,9 +209,7 @@ gsi_to_irq (unsigned int gsi)
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* and Linux irq numbers...
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*/
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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irq = _gsi_to_vector(gsi);
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}
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irq = _gsi_to_vector(gsi);
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return irq;
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@ -322,15 +320,12 @@ mask_irq (unsigned int irq)
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return; /* not an IOSAPIC interrupt! */
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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/* set only the mask bit */
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low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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/* set only the mask bit */
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low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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spin_unlock_irqrestore(&iosapic_lock, flags);
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}
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@ -349,14 +344,11 @@ unmask_irq (unsigned int irq)
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return; /* not an IOSAPIC interrupt! */
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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spin_unlock_irqrestore(&iosapic_lock, flags);
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}
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@ -391,28 +383,21 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
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high32 = dest << IOSAPIC_DEST_SHIFT;
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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low32 = iosapic_intr_info[vec].low32 &
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~(7 << IOSAPIC_DELIVERY_SHIFT);
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low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
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if (redir)
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/* change delivery mode to lowest priority */
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low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
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else
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/* change delivery mode to fixed */
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low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
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if (redir)
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/* change delivery mode to lowest priority */
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low32 |= (IOSAPIC_LOWEST_PRIORITY <<
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IOSAPIC_DELIVERY_SHIFT);
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else
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/* change delivery mode to fixed */
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low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
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iosapic_intr_info[vec].low32 = low32;
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iosapic_intr_info[vec].dest = dest;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index),
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high32);
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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iosapic_intr_info[vec].low32 = low32;
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iosapic_intr_info[vec].dest = dest;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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spin_unlock_irqrestore(&iosapic_lock, flags);
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#endif
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@ -797,14 +782,12 @@ iosapic_register_intr (unsigned int gsi,
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* don't touch the RTE.
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*/
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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vector = gsi_to_vector(gsi);
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if (vector > 0) {
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rte = gsi_vector_to_rte(gsi, vector);
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rte->refcnt++;
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return vector;
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}
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vector = gsi_to_vector(gsi);
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if (vector > 0) {
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rte = gsi_vector_to_rte(gsi, vector);
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rte->refcnt++;
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return vector;
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}
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spin_unlock_irqrestore(&iosapic_lock, flags);
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@ -818,35 +801,31 @@ iosapic_register_intr (unsigned int gsi,
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spin_lock_irqsave(&irq_desc[vector].lock, flags);
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spin_lock(&iosapic_lock);
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{
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if (gsi_to_vector(gsi) > 0) {
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if (list_empty(&iosapic_intr_info[vector].rtes))
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free_irq_vector(vector);
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spin_unlock(&iosapic_lock);
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spin_unlock_irqrestore(&irq_desc[vector].lock,
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flags);
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goto again;
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}
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dest = get_target_cpu(gsi, vector);
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err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
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polarity, trigger);
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if (err < 0) {
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spin_unlock(&iosapic_lock);
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spin_unlock_irqrestore(&irq_desc[vector].lock,
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flags);
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return err;
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}
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/*
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* If the vector is shared and already unmasked for
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* other interrupt sources, don't mask it.
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*/
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low32 = iosapic_intr_info[vector].low32;
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if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
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mask = 0;
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set_rte(gsi, vector, dest, mask);
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if (gsi_to_vector(gsi) > 0) {
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if (list_empty(&iosapic_intr_info[vector].rtes))
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free_irq_vector(vector);
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spin_unlock(&iosapic_lock);
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spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
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goto again;
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}
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dest = get_target_cpu(gsi, vector);
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err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
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polarity, trigger);
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if (err < 0) {
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spin_unlock(&iosapic_lock);
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spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
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return err;
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}
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/*
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* If the vector is shared and already unmasked for other
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* interrupt sources, don't mask it.
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*/
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low32 = iosapic_intr_info[vector].low32;
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if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
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mask = 0;
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set_rte(gsi, vector, dest, mask);
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spin_unlock(&iosapic_lock);
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spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
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@ -886,69 +865,64 @@ iosapic_unregister_intr (unsigned int gsi)
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idesc = irq_desc + irq;
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spin_lock_irqsave(&idesc->lock, flags);
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spin_lock(&iosapic_lock);
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{
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if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
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printk(KERN_ERR
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"iosapic_unregister_intr(%u) unbalanced\n",
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gsi);
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WARN_ON(1);
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goto out;
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}
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if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
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printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
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gsi);
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WARN_ON(1);
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goto out;
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}
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if (--rte->refcnt > 0)
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goto out;
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if (--rte->refcnt > 0)
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goto out;
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/* Mask the interrupt */
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low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
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iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index),
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low32);
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/* Mask the interrupt */
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low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
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iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
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/* Remove the rte entry from the list */
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list_del(&rte->rte_list);
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iosapic_intr_info[vector].count--;
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iosapic_free_rte(rte);
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index = find_iosapic(gsi);
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iosapic_lists[index].rtes_inuse--;
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WARN_ON(iosapic_lists[index].rtes_inuse < 0);
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/* Remove the rte entry from the list */
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list_del(&rte->rte_list);
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iosapic_intr_info[vector].count--;
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iosapic_free_rte(rte);
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index = find_iosapic(gsi);
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iosapic_lists[index].rtes_inuse--;
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WARN_ON(iosapic_lists[index].rtes_inuse < 0);
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trigger = iosapic_intr_info[vector].trigger;
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polarity = iosapic_intr_info[vector].polarity;
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dest = iosapic_intr_info[vector].dest;
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printk(KERN_INFO
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"GSI %u (%s, %s) -> CPU %d (0x%04x)"
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" vector %d unregistered\n",
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gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
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(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
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cpu_logical_id(dest), dest, vector);
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trigger = iosapic_intr_info[vector].trigger;
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polarity = iosapic_intr_info[vector].polarity;
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dest = iosapic_intr_info[vector].dest;
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printk(KERN_INFO
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"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
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gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
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(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
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cpu_logical_id(dest), dest, vector);
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if (list_empty(&iosapic_intr_info[vector].rtes)) {
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/* Sanity check */
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BUG_ON(iosapic_intr_info[vector].count);
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if (list_empty(&iosapic_intr_info[vector].rtes)) {
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/* Sanity check */
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BUG_ON(iosapic_intr_info[vector].count);
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/* Clear the interrupt controller descriptor */
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idesc->chip = &no_irq_type;
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/* Clear the interrupt controller descriptor */
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idesc->chip = &no_irq_type;
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#ifdef CONFIG_SMP
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/* Clear affinity */
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cpus_setall(idesc->affinity);
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/* Clear affinity */
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cpus_setall(idesc->affinity);
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#endif
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/* Clear the interrupt information */
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memset(&iosapic_intr_info[vector], 0,
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sizeof(struct iosapic_intr_info));
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iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
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INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
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/* Clear the interrupt information */
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memset(&iosapic_intr_info[vector], 0,
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sizeof(struct iosapic_intr_info));
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iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
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INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
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if (idesc->action) {
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printk(KERN_ERR
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"interrupt handlers still exist on"
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"IRQ %u\n", irq);
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WARN_ON(1);
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}
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/* Free the interrupt vector */
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free_irq_vector(vector);
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if (idesc->action) {
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printk(KERN_ERR
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"interrupt handlers still exist on IRQ %u\n",
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irq);
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WARN_ON(1);
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}
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/* Free the interrupt vector */
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free_irq_vector(vector);
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}
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out:
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spin_unlock(&iosapic_lock);
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@ -1108,31 +1082,29 @@ iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
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unsigned long flags;
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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addr = ioremap(phys_addr, 0);
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ver = iosapic_version(addr);
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addr = ioremap(phys_addr, 0);
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ver = iosapic_version(addr);
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if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
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iounmap(addr);
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return err;
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}
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/*
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* The MAX_REDIR register holds the highest input pin
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* number (starting from 0).
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* We add 1 so that we can use it for number of pins (= RTEs)
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*/
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num_rte = ((ver >> 16) & 0xff) + 1;
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index = iosapic_alloc();
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iosapic_lists[index].addr = addr;
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iosapic_lists[index].gsi_base = gsi_base;
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iosapic_lists[index].num_rte = num_rte;
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#ifdef CONFIG_NUMA
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iosapic_lists[index].node = MAX_NUMNODES;
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#endif
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if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
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iounmap(addr);
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return err;
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}
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/*
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* The MAX_REDIR register holds the highest input pin number
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* (starting from 0). We add 1 so that we can use it for
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* number of pins (= RTEs)
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*/
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num_rte = ((ver >> 16) & 0xff) + 1;
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index = iosapic_alloc();
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iosapic_lists[index].addr = addr;
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iosapic_lists[index].gsi_base = gsi_base;
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iosapic_lists[index].num_rte = num_rte;
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#ifdef CONFIG_NUMA
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iosapic_lists[index].node = MAX_NUMNODES;
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#endif
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spin_unlock_irqrestore(&iosapic_lock, flags);
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if ((gsi_base == 0) && pcat_compat) {
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@ -1157,25 +1129,22 @@ iosapic_remove (unsigned int gsi_base)
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unsigned long flags;
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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index = find_iosapic(gsi_base);
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if (index < 0) {
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printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
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__FUNCTION__, gsi_base);
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goto out;
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}
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if (iosapic_lists[index].rtes_inuse) {
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err = -EBUSY;
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printk(KERN_WARNING
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"%s: IOSAPIC for GSI base %u is busy\n",
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__FUNCTION__, gsi_base);
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goto out;
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}
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iounmap(iosapic_lists[index].addr);
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iosapic_free(index);
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index = find_iosapic(gsi_base);
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if (index < 0) {
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printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
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__FUNCTION__, gsi_base);
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goto out;
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}
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if (iosapic_lists[index].rtes_inuse) {
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err = -EBUSY;
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printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
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__FUNCTION__, gsi_base);
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goto out;
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}
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iounmap(iosapic_lists[index].addr);
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iosapic_free(index);
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out:
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spin_unlock_irqrestore(&iosapic_lock, flags);
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return err;
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