mirror of https://gitee.com/openkylin/linux.git
iommu/tegra-smmu: Convert to use DMA API
Use the DMA API instead of calling architecture internal functions in the Tegra SMMU driver. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Russell King
Thierry Reding
parent
d62c7a886c
commit
e3c971960f
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@ -16,8 +16,6 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <soc/tegra/ahb.h>
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#include <soc/tegra/mc.h>
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@ -45,6 +43,7 @@ struct tegra_smmu_as {
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u32 *count;
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struct page **pts;
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struct page *pd;
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dma_addr_t pd_dma;
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unsigned id;
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u32 attr;
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};
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@ -82,9 +81,9 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
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#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
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#define SMMU_PTB_DATA 0x020
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#define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr))
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#define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
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#define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr))
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#define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
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#define SMMU_TLB_FLUSH 0x030
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#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
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@ -147,22 +146,15 @@ static unsigned int iova_pt_index(unsigned long iova)
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return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
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}
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static void smmu_flush_dcache(struct page *page, unsigned long offset,
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size_t size)
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static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
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{
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#ifdef CONFIG_ARM
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phys_addr_t phys = page_to_phys(page) + offset;
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#endif
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void *virt = page_address(page) + offset;
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addr >>= 12;
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return (addr & smmu->pfn_mask) == addr;
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}
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#ifdef CONFIG_ARM
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__cpuc_flush_dcache_area(virt, size);
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outer_flush_range(phys, phys + size);
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#endif
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#ifdef CONFIG_ARM64
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__flush_dcache_area(virt, size);
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#endif
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static dma_addr_t smmu_pde_to_dma(u32 pde)
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{
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return pde << 12;
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}
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static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
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@ -170,7 +162,7 @@ static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
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smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
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}
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static inline void smmu_flush_ptc(struct tegra_smmu *smmu, phys_addr_t phys,
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static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
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unsigned long offset)
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{
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u32 value;
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@ -178,15 +170,15 @@ static inline void smmu_flush_ptc(struct tegra_smmu *smmu, phys_addr_t phys,
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offset &= ~(smmu->mc->soc->atom_size - 1);
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if (smmu->mc->soc->num_address_bits > 32) {
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
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#else
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value = 0;
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#endif
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smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
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}
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value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
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value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
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smmu_writel(smmu, value, SMMU_PTC_FLUSH);
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}
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@ -407,16 +399,26 @@ static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
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return 0;
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}
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as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
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DMA_TO_DEVICE);
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if (dma_mapping_error(smmu->dev, as->pd_dma))
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return -ENOMEM;
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/* We can't handle 64-bit DMA addresses */
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if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
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err = -ENOMEM;
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goto err_unmap;
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}
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err = tegra_smmu_alloc_asid(smmu, &as->id);
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if (err < 0)
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return err;
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goto err_unmap;
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smmu_flush_dcache(as->pd, 0, SMMU_SIZE_PD);
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smmu_flush_ptc(smmu, page_to_phys(as->pd), 0);
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smmu_flush_ptc(smmu, as->pd_dma, 0);
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smmu_flush_tlb_asid(smmu, as->id);
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smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
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value = SMMU_PTB_DATA_VALUE(as->pd, as->attr);
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value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
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smmu_writel(smmu, value, SMMU_PTB_DATA);
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smmu_flush(smmu);
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@ -424,6 +426,10 @@ static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
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as->use_count++;
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return 0;
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err_unmap:
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dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
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return err;
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}
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static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
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@ -433,6 +439,9 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
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return;
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tegra_smmu_free_asid(smmu, as->id);
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dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
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as->smmu = NULL;
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}
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@ -504,63 +513,81 @@ static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
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}
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static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
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struct page **pagep)
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dma_addr_t *dmap)
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{
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unsigned int pd_index = iova_pd_index(iova);
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struct page *pt_page;
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u32 *pd;
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pt_page = as->pts[pd_index];
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if (!pt_page)
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return NULL;
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*pagep = pt_page;
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pd = page_address(as->pd);
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*dmap = smmu_pde_to_dma(pd[pd_index]);
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return tegra_smmu_pte_offset(pt_page, iova);
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}
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static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
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struct page **pagep)
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dma_addr_t *dmap)
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{
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u32 *pd = page_address(as->pd), *pt;
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unsigned int pde = iova_pd_index(iova);
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struct tegra_smmu *smmu = as->smmu;
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struct page *page;
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unsigned int i;
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if (!as->pts[pde]) {
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struct page *page;
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dma_addr_t dma;
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page = alloc_page(GFP_KERNEL | __GFP_DMA);
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if (!page)
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return NULL;
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pt = page_address(page);
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SetPageReserved(page);
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for (i = 0; i < SMMU_NUM_PTE; i++)
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pt[i] = 0;
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dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
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DMA_TO_DEVICE);
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if (dma_mapping_error(smmu->dev, dma)) {
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__free_page(page);
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return NULL;
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}
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if (!smmu_dma_addr_valid(smmu, dma)) {
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dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
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DMA_TO_DEVICE);
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__free_page(page);
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return NULL;
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}
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as->pts[pde] = page;
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smmu_flush_dcache(page, 0, SMMU_SIZE_PT);
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SetPageReserved(page);
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pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT);
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pd[pde] = SMMU_MK_PDE(dma, SMMU_PDE_ATTR | SMMU_PDE_NEXT);
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smmu_flush_dcache(as->pd, pde << 2, 4);
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smmu_flush_ptc(smmu, page_to_phys(as->pd), pde << 2);
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dma_sync_single_range_for_device(smmu->dev, as->pd_dma,
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pde << 2, 4, DMA_TO_DEVICE);
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smmu_flush_ptc(smmu, as->pd_dma, pde << 2);
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smmu_flush_tlb_section(smmu, as->id, iova);
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smmu_flush(smmu);
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*dmap = dma;
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} else {
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page = as->pts[pde];
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*dmap = smmu_pde_to_dma(pd[pde]);
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}
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*pagep = page;
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pt = page_address(page);
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pt = tegra_smmu_pte_offset(as->pts[pde], iova);
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/* Keep track of entries in this page table. */
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if (pt[iova_pt_index(iova)] == 0)
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if (*pt == 0)
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as->count[pde]++;
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return tegra_smmu_pte_offset(page, iova);
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return pt;
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}
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static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
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@ -576,17 +603,20 @@ static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
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*/
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if (--as->count[pde] == 0) {
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unsigned int offset = pde * sizeof(*pd);
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dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]);
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/* Clear the page directory entry first */
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pd[pde] = 0;
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/* Flush the page directory entry */
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smmu_flush_dcache(as->pd, offset, sizeof(*pd));
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smmu_flush_ptc(smmu, page_to_phys(as->pd), offset);
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dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
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sizeof(*pd), DMA_TO_DEVICE);
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smmu_flush_ptc(smmu, as->pd_dma, offset);
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smmu_flush_tlb_section(smmu, as->id, iova);
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smmu_flush(smmu);
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/* Finally, free the page */
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dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
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ClearPageReserved(page);
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__free_page(page);
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as->pts[pde] = NULL;
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@ -594,15 +624,16 @@ static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
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}
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static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
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u32 *pte, struct page *pte_page, u32 val)
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u32 *pte, dma_addr_t pte_dma, u32 val)
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{
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struct tegra_smmu *smmu = as->smmu;
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unsigned long offset = offset_in_page(pte);
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*pte = val;
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smmu_flush_dcache(pte_page, offset, 4);
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smmu_flush_ptc(smmu, page_to_phys(pte_page), offset);
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dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
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4, DMA_TO_DEVICE);
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smmu_flush_ptc(smmu, pte_dma, offset);
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smmu_flush_tlb_group(smmu, as->id, iova);
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smmu_flush(smmu);
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}
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@ -611,14 +642,14 @@ static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot)
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{
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struct tegra_smmu_as *as = to_smmu_as(domain);
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struct page *page;
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dma_addr_t pte_dma;
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u32 *pte;
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pte = as_get_pte(as, iova, &page);
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pte = as_get_pte(as, iova, &pte_dma);
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if (!pte)
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return -ENOMEM;
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tegra_smmu_set_pte(as, iova, pte, page,
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tegra_smmu_set_pte(as, iova, pte, pte_dma,
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__phys_to_pfn(paddr) | SMMU_PTE_ATTR);
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return 0;
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@ -628,14 +659,14 @@ static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t size)
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{
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struct tegra_smmu_as *as = to_smmu_as(domain);
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struct page *pte_page;
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dma_addr_t pte_dma;
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u32 *pte;
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pte = tegra_smmu_pte_lookup(as, iova, &pte_page);
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pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
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if (!pte || !*pte)
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return 0;
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tegra_smmu_set_pte(as, iova, pte, pte_page, 0);
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tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
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tegra_smmu_pte_put_use(as, iova);
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return size;
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@ -645,11 +676,11 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct tegra_smmu_as *as = to_smmu_as(domain);
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struct page *pte_page;
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unsigned long pfn;
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dma_addr_t pte_dma;
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u32 *pte;
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pte = tegra_smmu_pte_lookup(as, iova, &pte_page);
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pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
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if (!pte || !*pte)
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return 0;
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