mirror of https://gitee.com/openkylin/linux.git
ARM: shmobile: Initial r7s72100 SoC support
Add initial support for the r7272100 SoC including: - Single Cortex-A9 CPU Core - GIC No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm
Simon Horman
parent
cd8344f4dd
commit
e3da5b36d4
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@ -0,0 +1,36 @@
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/*
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* Device Tree Source for the r7s72100 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r7s72100";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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gic: interrupt-controller@e8201000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8201000 0x1000>,
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<0xe8202000 0x1000>;
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};
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};
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@ -113,6 +113,12 @@ config ARCH_EMEV2
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select ARM_GIC
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select CPU_V7
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config ARCH_R7S72100
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bool "RZ/A1H (R7S72100)"
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select ARM_GIC
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select CPU_V7
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select SH_CLK_CPG
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comment "SH-Mobile Board Type"
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config MACH_APE6EVM
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@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o
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obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
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# Clock objects
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ifndef CONFIG_COMMON_CLK
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@ -31,6 +32,7 @@ obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
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obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o
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endif
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# SMP objects
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@ -0,0 +1,194 @@
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/*
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* r7a72100 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2012 Phil Edworthy
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#include <mach/r7s72100.h>
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/* registers */
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#define FRQCR 0xfcfe0010
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#define FRQCR2 0xfcfe0014
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#define STBCR3 0xfcfe0420
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#define STBCR4 0xfcfe0424
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#define PLL_RATE 30
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static struct clk_mapping cpg_mapping = {
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.phys = 0xfcfe0000,
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.len = 0x1000,
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};
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/* Fixed 32 KHz root clock for RTC */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 13330000,
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.mapping = &cpg_mapping,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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return clk->parent->rate * PLL_RATE;
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long bus_recalc(struct clk *clk)
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{
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return clk->parent->rate * 2 / 3;
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}
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static struct sh_clk_ops bus_clk_ops = {
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.recalc = bus_recalc,
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};
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static struct clk bus_clk = {
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.ops = &bus_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long peripheral0_recalc(struct clk *clk)
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{
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return clk->parent->rate / 12;
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}
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static struct sh_clk_ops peripheral0_clk_ops = {
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.recalc = peripheral0_recalc,
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};
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static struct clk peripheral0_clk = {
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.ops = &peripheral0_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long peripheral1_recalc(struct clk *clk)
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{
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return clk->parent->rate / 6;
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}
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static struct sh_clk_ops peripheral1_clk_ops = {
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.recalc = peripheral1_recalc,
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};
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static struct clk peripheral1_clk = {
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.ops = &peripheral1_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&pll_clk,
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&bus_clk,
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&peripheral0_clk,
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&peripheral1_clk,
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};
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static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
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static int multipliers[] = { 1, 2, 1, 1 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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.multipliers = multipliers,
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.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I,
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DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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/* The mask field specifies the div2 entries that are valid */
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
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| CLK_ENABLE_ON_INIT),
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};
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enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
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MSTP33, MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
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[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
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[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
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[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
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[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
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[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
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[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
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[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
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[MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP clocks */
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};
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void __init r7s72100_clock_init(void)
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{
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int k, ret = 0;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup rza1 clocks\n");
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}
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@ -0,0 +1,7 @@
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#ifndef __ASM_R7S72100_H__
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#define __ASM_R7S72100_H__
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void r7s72100_clock_init(void);
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void r7s72100_init_early(void);
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#endif /* __ASM_R7S72100_H__ */
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@ -0,0 +1,43 @@
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/*
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* r7s72100 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <mach/common.h>
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#include <mach/r7s72100.h>
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#include <asm/mach/arch.h>
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void __init r7s72100_init_early(void)
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{
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shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */
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}
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#ifdef CONFIG_USE_OF
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static const char *r7s72100_boards_compat_dt[] __initdata = {
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"renesas,r7s72100",
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NULL,
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};
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DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
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.init_early = r7s72100_init_early,
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.dt_compat = r7s72100_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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