mirror of https://gitee.com/openkylin/linux.git
ath10k: convert ath10k_pci_reg_read/write32() to take struct ath10k
This is consistent with all other functions. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -2323,18 +2323,13 @@ static int ath10k_pci_reset_target(struct ath10k *ar)
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static void ath10k_pci_device_reset(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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void __iomem *mem = ar_pci->mem;
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int i;
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u32 val;
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if (!SOC_GLOBAL_RESET_ADDRESS)
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return;
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if (!mem)
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return;
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ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS,
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ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
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PCIE_SOC_WAKE_V_MASK);
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for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
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if (ath10k_pci_target_is_awake(ar))
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@ -2343,12 +2338,12 @@ static void ath10k_pci_device_reset(struct ath10k *ar)
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}
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/* Put Target, including PCIe, into RESET. */
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val = ath10k_pci_reg_read32(mem, SOC_GLOBAL_RESET_ADDRESS);
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val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
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val |= 1;
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ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
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ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
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for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
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if (ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
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if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
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RTC_STATE_COLD_RESET_MASK)
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break;
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msleep(1);
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@ -2356,16 +2351,16 @@ static void ath10k_pci_device_reset(struct ath10k *ar)
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/* Pull Target, including PCIe, out of RESET. */
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val &= ~1;
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ath10k_pci_reg_write32(mem, SOC_GLOBAL_RESET_ADDRESS, val);
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ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
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for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
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if (!(ath10k_pci_reg_read32(mem, RTC_STATE_ADDRESS) &
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if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
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RTC_STATE_COLD_RESET_MASK))
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break;
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msleep(1);
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}
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ath10k_pci_reg_write32(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
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ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
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}
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static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
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@ -240,14 +240,18 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
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return ar->hif.priv;
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}
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static inline u32 ath10k_pci_reg_read32(void __iomem *mem, u32 addr)
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static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
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{
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return ioread32(mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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}
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static inline void ath10k_pci_reg_write32(void __iomem *mem, u32 addr, u32 val)
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static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
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{
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iowrite32(val, mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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}
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#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
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