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KVM: PIC: enhance IPI avoidance 

The PIC code makes little effort to avoid kvm_vcpu_kick(), resulting in
unnecessary guest exits in some conditions.

For example, if the timer interrupt is routed through the IOAPIC, IRR
for IRQ 0 will get set but not cleared, since the APIC is handling the
acks.

This means that everytime an interrupt < 16 is triggered, the priority
logic will find IRQ0 pending and send an IPI to vcpu0 (in case IRQ0 is
not masked, which is Linux's case).

Introduce a new variable isr_ack to represent the IRQ's for which the
guest has been signalled / cleared the ISR. Use it to avoid more than
one IPI per trigger-ack cycle, in addition to the avoidance when ISR is
set in get_priority().

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Marcelo Tosatti 2008-09-24 20:28:34 -03:00 committed by Avi Kivity
parent 582801a95d
commit e48258009d
3 changed files with 18 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/x86/kvm/i8259.c
View File

@ -33,6 +33,14 @@
static void pic_clear_isr(struct kvm_kpic_state *s, int irq) static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
{ {
s->isr &= ~(1 << irq); s->isr &= ~(1 << irq);
s->isr_ack |= (1 << irq);
}
void kvm_pic_clear_isr_ack(struct kvm *kvm)
{
struct kvm_pic *s = pic_irqchip(kvm);
s->pics[0].isr_ack = 0xff;
s->pics[1].isr_ack = 0xff;
} }
/* /*
@ -213,6 +221,7 @@ void kvm_pic_reset(struct kvm_kpic_state *s)
s->irr = 0; s->irr = 0;
s->imr = 0; s->imr = 0;
s->isr = 0; s->isr = 0;
s->isr_ack = 0xff;
s->priority_add = 0; s->priority_add = 0;
s->irq_base = 0; s->irq_base = 0;
s->read_reg_select = 0; s->read_reg_select = 0;
@ -444,10 +453,14 @@ static void pic_irq_request(void *opaque, int level)
{ {
struct kvm *kvm = opaque; struct kvm *kvm = opaque;
struct kvm_vcpu *vcpu = kvm->vcpus[0]; struct kvm_vcpu *vcpu = kvm->vcpus[0];
struct kvm_pic *s = pic_irqchip(kvm);
int irq = pic_get_irq(&s->pics[0]);
pic_irqchip(kvm)->output = level; s->output = level;
if (vcpu) if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
s->pics[0].isr_ack &= ~(1 << irq);
kvm_vcpu_kick(vcpu); kvm_vcpu_kick(vcpu);
}
} }
struct kvm_pic *kvm_create_pic(struct kvm *kvm) struct kvm_pic *kvm_create_pic(struct kvm *kvm)

2
arch/x86/kvm/irq.h
View File

@ -42,6 +42,7 @@ struct kvm_kpic_state {
u8 irr; /* interrupt request register */ u8 irr; /* interrupt request register */
u8 imr; /* interrupt mask register */ u8 imr; /* interrupt mask register */
u8 isr; /* interrupt service register */ u8 isr; /* interrupt service register */
u8 isr_ack; /* interrupt ack detection */
u8 priority_add; /* highest irq priority */ u8 priority_add; /* highest irq priority */
u8 irq_base; u8 irq_base;
u8 read_reg_select; u8 read_reg_select;
@ -70,6 +71,7 @@ struct kvm_pic *kvm_create_pic(struct kvm *kvm);
void kvm_pic_set_irq(void *opaque, int irq, int level); void kvm_pic_set_irq(void *opaque, int irq, int level);
int kvm_pic_read_irq(struct kvm *kvm); int kvm_pic_read_irq(struct kvm *kvm);
void kvm_pic_update_irq(struct kvm_pic *s); void kvm_pic_update_irq(struct kvm_pic *s);
void kvm_pic_clear_isr_ack(struct kvm *kvm);
static inline struct kvm_pic *pic_irqchip(struct kvm *kvm) static inline struct kvm_pic *pic_irqchip(struct kvm *kvm)
{ {

1
arch/x86/kvm/x86.c
View File

@ -3963,6 +3963,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
pr_debug("Set back pending irq %d\n", pr_debug("Set back pending irq %d\n",
pending_vec); pending_vec);
} }
kvm_pic_clear_isr_ack(vcpu->kvm);
} }
kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);