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spi: spi-sh-msiof: round up div to fix freq calculation 

Truncation on integer division in sh_msiof_spi_set_clk_regs()
results in insufficient transfer frequency (> max_speed_freq).

For example, source 52MHz, required max 6MHz
 52/6 = 8.6 --> 8, then 1/8 table selected,
and result in 52/8 = 6.5 MHz (>6MHz)

Rounding it up is a simple solution.
 52/6 = 8.6 --> 9, then 1/16 table selected,
and result in 52/16 = 3.25 MHz

Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Takashi Yoshii 2013-12-02 03:19:13 +09:00 committed by Mark Brown
parent 6ce4eac1f6
commit e4d313ff79
1 changed files with 1 additions and 1 deletions
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2
drivers/spi/spi-sh-msiof.c
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@ -152,7 +152,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
size_t k;
if (!WARN_ON(!spi_hz || !parent_rate))
div = parent_rate / spi_hz;
div = DIV_ROUND_UP(parent_rate, spi_hz);
/* TODO: make more fine grained */