mirror of https://gitee.com/openkylin/linux.git
drm/i915: introduce crtc->dspaddr_offset
To avoid recomputing the display framebuffer offset on gen2/3 pageflips. This is also prep work to do similar trickery on gen4+ Also: - kill "Start", such upper-case remnants from the ddx must surely die. - rename "Offset" to linear_offset, to make it clearer that on gen4+ this is only used by the hw for linear buffers, for tiled buffers it uses the TILEOFF register. - call DSAPADDR DSPLINOFF on gen4+ for the same reason (and because the documentation really renamed the register). Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
e6a595d2db
commit
e506a0c638
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@ -2979,6 +2979,7 @@
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#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
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#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
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#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
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#define DSPLINOFF(plane) DSPADDR(plane)
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/* Display/Sprite base address macros */
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#define DISP_BASEADDR_MASK (0xfffff000)
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@ -1982,7 +1982,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct intel_framebuffer *intel_fb;
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struct drm_i915_gem_object *obj;
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int plane = intel_crtc->plane;
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unsigned long Start, Offset;
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unsigned long linear_offset;
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u32 dspcntr;
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u32 reg;
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@ -2029,18 +2029,22 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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I915_WRITE(reg, dspcntr);
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Start = obj->gtt_offset;
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Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
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Start, Offset, x, y, fb->pitches[0]);
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if (INTEL_INFO(dev)->gen >= 4)
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intel_crtc->dspaddr_offset = 0;
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else
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intel_crtc->dspaddr_offset = linear_offset;
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DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
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obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
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I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
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if (INTEL_INFO(dev)->gen >= 4) {
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I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
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I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset);
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I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
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I915_WRITE(DSPADDR(plane), Offset);
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I915_WRITE(DSPLINOFF(plane), linear_offset);
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} else
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I915_WRITE(DSPADDR(plane), Start + Offset);
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I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
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POSTING_READ(reg);
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return 0;
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@ -2055,7 +2059,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
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struct intel_framebuffer *intel_fb;
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struct drm_i915_gem_object *obj;
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int plane = intel_crtc->plane;
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unsigned long Start, Offset;
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unsigned long linear_offset;
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u32 dspcntr;
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u32 reg;
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@ -2110,15 +2114,15 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
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I915_WRITE(reg, dspcntr);
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Start = obj->gtt_offset;
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Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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intel_crtc->dspaddr_offset = 0;
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DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
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Start, Offset, x, y, fb->pitches[0]);
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DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
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obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
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I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
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I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
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I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset);
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I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
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I915_WRITE(DSPADDR(plane), Offset);
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I915_WRITE(DSPLINOFF(plane), linear_offset);
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POSTING_READ(reg);
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return 0;
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@ -6194,7 +6198,6 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long offset;
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u32 flip_mask;
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struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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int ret;
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@ -6203,9 +6206,6 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
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if (ret)
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goto err;
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
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ret = intel_ring_begin(ring, 6);
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if (ret)
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goto err_unpin;
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@ -6222,7 +6222,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
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intel_ring_emit(ring, MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(ring, fb->pitches[0]);
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intel_ring_emit(ring, obj->gtt_offset + offset);
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intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
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intel_ring_emit(ring, 0); /* aux display base address, unused */
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intel_ring_advance(ring);
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return 0;
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@ -6240,7 +6240,6 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long offset;
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u32 flip_mask;
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struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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int ret;
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@ -6249,9 +6248,6 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
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if (ret)
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goto err;
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
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ret = intel_ring_begin(ring, 6);
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if (ret)
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goto err_unpin;
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@ -6265,7 +6261,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
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intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(ring, fb->pitches[0]);
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intel_ring_emit(ring, obj->gtt_offset + offset);
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intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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@ -177,6 +177,11 @@ struct intel_crtc {
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struct intel_unpin_work *unpin_work;
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int fdi_lanes;
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/* Display surface base address adjustement for pageflips. Note that on
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* gen4+ this only adjusts up to a tile, offsets within a tile are
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* handled in the hw itself (with the TILEOFF register). */
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unsigned long dspaddr_offset;
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struct drm_i915_gem_object *cursor_bo;
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uint32_t cursor_addr;
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int16_t cursor_x, cursor_y;
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