mirror of https://gitee.com/openkylin/linux.git
mmc: remove dw_mmc-zx driver
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120142801.334550-2-arnd@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Arnd Bergmann
Ulf Hansson
parent
fe6e147178
commit
e55f2cf512
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@ -1,31 +0,0 @@
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* ZTE specific extensions to the Synopsys Designware Mobile Storage
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Host Controller
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The Synopsys designware mobile storage host controller is used to interface
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a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
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differences between the core Synopsys dw mshc controller properties described
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by synopsys-dw-mshc.txt and the properties used by the ZTE specific
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extensions to the Synopsys Designware Mobile Storage Host Controller.
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Required Properties:
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* compatible: should be
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- "zte,zx296718-dw-mshc": for ZX SoCs
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Example:
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mmc1: mmc@1110000 {
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compatible = "zte,zx296718-dw-mshc";
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reg = <0x01110000 0x1000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <32>;
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data-addr = <0x200>;
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fifo-watermark-aligned;
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bus-width = <4>;
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clock-frequency = <50000000>;
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clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
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clock-names = "biu", "ciu";
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max-frequency = <50000000>;
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cap-sdio-irq;
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cap-sd-highspeed;
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};
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@ -882,15 +882,6 @@ config MMC_DW_ROCKCHIP
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on RK3066, RK3188 and RK3288 SoC's.
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config MMC_DW_ZX
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tristate "ZTE specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW && ARCH_ZX
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select MMC_DW_PLTFM
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help
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This selects support for ZTE SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on ZX296718 SoC's.
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config MMC_SH_MMCIF
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tristate "SuperH Internal MMCIF support"
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depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
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@ -61,7 +61,6 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
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obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
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obj-$(CONFIG_MMC_DW_ZX) += dw_mmc-zx.o
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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obj-$(CONFIG_MMC_VUB300) += vub300.o
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@ -1,234 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2016, Linaro Ltd.
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* Copyright (C) 2016, ZTE Corp.
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#include "dw_mmc-zx.h"
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struct dw_mci_zx_priv_data {
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struct regmap *sysc_base;
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};
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enum delay_type {
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DELAY_TYPE_READ, /* read dqs delay */
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DELAY_TYPE_CLK, /* clk sample delay */
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};
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static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
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enum delay_type dflag)
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{
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struct dw_mci_zx_priv_data *priv = host->priv;
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struct regmap *sysc_base = priv->sysc_base;
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unsigned int clksel;
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unsigned int loop = 1000;
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int ret;
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if (!sysc_base)
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return -EINVAL;
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ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
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PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE |
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PARA_PHASE_DET_SEL_MASK |
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PARA_DLL_LOCK_NUM_MASK |
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DLL_REG_SET | PARA_DLL_START_MASK,
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PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4));
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if (ret)
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return ret;
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ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
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if (ret)
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return ret;
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if (dflag == DELAY_TYPE_CLK) {
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clksel &= ~CLK_SAMP_DELAY_MASK;
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clksel |= CLK_SAMP_DELAY(delay);
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} else {
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clksel &= ~READ_DQS_DELAY_MASK;
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clksel |= READ_DQS_DELAY(delay);
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}
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regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
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regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
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PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK |
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DLL_REG_SET,
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PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) |
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DLL_REG_SET);
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do {
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ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
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if (ret)
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return ret;
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} while (--loop && !(clksel & ZX_DLL_LOCKED));
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if (!loop) {
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dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
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return -EIO;
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}
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return 0;
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}
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static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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struct dw_mci *host = slot->host;
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struct mmc_host *mmc = slot->mmc;
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int ret, len = 0, start = 0, end = 0, delay, best = 0;
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for (delay = 1; delay < 128; delay++) {
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ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
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if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
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if (start >= 0) {
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end = delay - 1;
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/* check and update longest good range */
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if ((end - start) > len) {
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best = (start + end) >> 1;
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len = end - start;
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}
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}
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start = -1;
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end = 0;
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continue;
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}
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if (start < 0)
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start = delay;
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}
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if (start >= 0) {
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end = delay - 1;
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if ((end - start) > len) {
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best = (start + end) >> 1;
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len = end - start;
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}
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}
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if (best < 0)
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return -EIO;
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dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
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start, end);
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return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
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}
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static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
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struct mmc_ios *ios)
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{
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int ret;
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/* config phase shift as 90 degree */
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ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
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if (ret < 0)
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return -EIO;
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return 0;
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}
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static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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struct dw_mci *host = slot->host;
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if (host->verid == 0x290a) /* only for emmc */
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return dw_mci_zx_emmc_execute_tuning(slot, opcode);
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/* TODO: Add 0x210a dedicated tuning for sd/sdio */
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return 0;
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}
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static int dw_mci_zx_parse_dt(struct dw_mci *host)
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{
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struct device_node *np = host->dev->of_node;
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struct device_node *node;
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struct dw_mci_zx_priv_data *priv;
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struct regmap *sysc_base;
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/* syscon is needed only by emmc */
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node = of_parse_phandle(np, "zte,aon-syscon", 0);
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if (node) {
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sysc_base = syscon_node_to_regmap(node);
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of_node_put(node);
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if (IS_ERR(sysc_base))
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return dev_err_probe(host->dev, PTR_ERR(sysc_base),
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"Can't get syscon\n");
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} else {
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return 0;
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}
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->sysc_base = sysc_base;
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host->priv = priv;
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return 0;
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}
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static unsigned long zx_dwmmc_caps[3] = {
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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};
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static const struct dw_mci_drv_data zx_drv_data = {
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.caps = zx_dwmmc_caps,
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.num_caps = ARRAY_SIZE(zx_dwmmc_caps),
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.execute_tuning = dw_mci_zx_execute_tuning,
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.prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
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.parse_dt = dw_mci_zx_parse_dt,
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};
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static const struct of_device_id dw_mci_zx_match[] = {
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{ .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_zx_match);
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static int dw_mci_zx_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
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dw_mci_runtime_resume,
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NULL)
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};
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static struct platform_driver dw_mci_zx_pltfm_driver = {
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.probe = dw_mci_zx_probe,
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.remove = dw_mci_pltfm_remove,
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.driver = {
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.name = "dwmmc_zx",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = dw_mci_zx_match,
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.pm = &dw_mci_zx_dev_pm_ops,
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},
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};
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module_platform_driver(dw_mci_zx_pltfm_driver);
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MODULE_DESCRIPTION("ZTE emmc/sd driver");
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MODULE_LICENSE("GPL v2");
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@ -1,32 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _DW_MMC_ZX_H_
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#define _DW_MMC_ZX_H_
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/* ZX296718 SoC specific DLL register offset. */
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#define LB_AON_EMMC_CFG_REG0 0x1B0
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#define LB_AON_EMMC_CFG_REG1 0x1B4
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#define LB_AON_EMMC_CFG_REG2 0x1B8
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/* LB_AON_EMMC_CFG_REG0 register defines */
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#define PARA_DLL_START(x) ((x) & 0xFF)
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#define PARA_DLL_START_MASK 0xFF
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#define DLL_REG_SET BIT(8)
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#define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16)
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#define PARA_DLL_LOCK_NUM_MASK (7 << 16)
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#define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20)
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#define PARA_PHASE_DET_SEL_MASK (7 << 20)
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#define PARA_DLL_BYPASS_MODE BIT(23)
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#define PARA_HALF_CLK_MODE BIT(24)
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/* LB_AON_EMMC_CFG_REG1 register defines */
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#define READ_DQS_DELAY(x) ((x) & 0x7F)
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#define READ_DQS_DELAY_MASK (0x7F)
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#define READ_DQS_BYPASS_MODE BIT(7)
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#define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)
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#define CLK_SAMP_DELAY_MASK (0x7F << 8)
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#define CLK_SAMP_BYPASS_MODE BIT(15)
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/* LB_AON_EMMC_CFG_REG2 register defines */
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#define ZX_DLL_LOCKED BIT(2)
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#endif /* _DW_MMC_ZX_H_ */
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