The POWER9 hardware has dropped support for several events, added
a few new events and changed the category for a couple of events.
Update the POWER9 events in Linux to reflect these changes.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20171108201938.GA10985@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sukadev Bhattiprolu2017-11-08 18:42:03 -05:00committed byArnaldo Carvalho de Melo
"BriefDescription":"TM marked store abort for this thread"
},
{,
"EventCode":"0x25044",
"EventName":"PM_IPTEG_FROM_L31_MOD",
@ -369,4 +364,4 @@
"EventName":"PM_IPTEG_FROM_L31_ECO_MOD",
"BriefDescription":"A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"
"BriefDescription":"Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{,
"EventCode":"0x3013E",
"EventName":"PM_MRK_STALL_CMPLU_CYC",
@ -254,6 +249,11 @@
"EventName":"PM_RADIX_PWC_L1_PDE_FROM_L3",
"BriefDescription":"A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache"
},
{,
"EventCode":"0x3C052",
"EventName":"PM_DATA_SYS_PUMP_MPRED",
"BriefDescription":"Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{,
"EventCode":"0x4D142",
"EventName":"PM_MRK_DATA_FROM_L3",
@ -434,21 +434,6 @@
"EventName":"PM_ITLB_MISS",
"BriefDescription":"ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed"
},
{,
"EventCode":"0x2D024",
"EventName":"PM_RADIX_PWC_L2_HIT",
"BriefDescription":"A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache."
},
{,
"EventCode":"0x3F056",
"EventName":"PM_RADIX_PWC_L3_HIT",
"BriefDescription":"A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache."
},
{,
"EventCode":"0x4E014",
"EventName":"PM_TM_TX_PASS_RUN_INST",
"BriefDescription":"Run instructions spent in successful transactions"
"BriefDescription":"A radix translation attempt missed in the TLB and all levels of page walk cache."
},
{,
"EventCode":"0x26882",
"EventName":"PM_L2_DC_INV",
"BriefDescription":"D-cache invalidates sent over the reload bus to the core"
},
{,
"EventCode":"0x24048",
"EventName":"PM_INST_FROM_LMEM",
@ -94,11 +99,6 @@
"EventName":"PM_TM_PASSED",
"BriefDescription":"Number of TM transactions that passed"
},
{,
"EventCode":"0xD1A0",
"EventName":"PM_MRK_LSU_FLUSH_LHS",
"BriefDescription":"Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed"
},
{,
"EventCode":"0xF088",
"EventName":"PM_LSU0_STORE_REJECT",
@ -127,7 +127,7 @@
{,
"EventCode":"0xD08C",
"EventName":"PM_LSU2_LDMX_FIN",
"BriefDescription":"New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])"
"BriefDescription":"New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])."
},
{,
"EventCode":"0x300F8",
@ -204,11 +204,6 @@
"EventName":"PM_MRK_DATA_FROM_L31_ECO_MOD_CYC",
"BriefDescription":"Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
"EventCode":"0xF0B4",
"EventName":"PM_DC_PREF_CONS_ALLOC",
"BriefDescription":"Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch"
},
{,
"EventCode":"0xF894",
"EventName":"PM_LSU3_L1_CAM_CANCEL",
@ -219,21 +214,11 @@
"EventName":"PM_FLUSH_DISP_TLBIE",
"BriefDescription":"Dispatch Flush: TLBIE"
},
{,
"EventCode":"0xD1A4",
"EventName":"PM_MRK_LSU_FLUSH_SAO",
"BriefDescription":"A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush"
},
{,
"EventCode":"0x4E11E",
"EventName":"PM_MRK_DATA_FROM_DMEM_CYC",
"BriefDescription":"Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
},
{,
"EventCode":"0x5894",
"EventName":"PM_LWSYNC",
"BriefDescription":"Lwsync instruction decoded and transferred"
},
{,
"EventCode":"0x14156",
"EventName":"PM_MRK_DATA_FROM_L2_CYC",
@ -244,11 +229,6 @@
"EventName":"PM_RD_CLEARING_SC",
"BriefDescription":"Read clearing SC"
},
{,
"EventCode":"0x50A0",
"EventName":"PM_HWSYNC",
"BriefDescription":"Hwsync instruction decoded and transferred"
"BriefDescription":"The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load"
},
{,
"EventCode":"0x468AE",
"EventName":"PM_L3_P3_CO_RTY",
"BriefDescription":"L3 CO received retry port 3 (memory only), every retry counted"
},
{,
"EventCode":"0x460A8",
"EventName":"PM_SN_HIT",
@ -279,11 +264,6 @@
"EventName":"PM_DC_PREF_HW_ALLOC",
"BriefDescription":"Prefetch stream allocated by the hardware prefetch mechanism"
},
{,
"EventCode":"0xF0BC",
"EventName":"PM_LS2_UNALIGNED_ST",
"BriefDescription":"Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0xD0AC",
"EventName":"PM_SRQ_SYNC_CYC",
@ -379,26 +359,11 @@
"EventName":"PM_RUN_CYC_SMT4_MODE",
"BriefDescription":"Cycles in which this thread's run latch is set and the core is in SMT4 mode"
},
{,
"EventCode":"0x5088",
"EventName":"PM_DECODE_FUSION_OP_PRESERV",
"BriefDescription":"Destructive op operand preservation"
"BriefDescription":"Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
},
{,
"EventCode":"0x509C",
"EventName":"PM_FORCED_NOP",
"BriefDescription":"Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time"
},
{,
"EventCode":"0xC098",
"EventName":"PM_LS2_UNALIGNED_LD",
"BriefDescription":"Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0x20058",
"EventName":"PM_DARQ1_10_12_ENTRIES",
@ -434,11 +399,6 @@
"EventName":"PM_LSU1_STORE_REJECT",
"BriefDescription":"All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met"
},
{,
"EventCode":"0x4505E",
"EventName":"PM_FLOP_CMPL",
"BriefDescription":"Floating Point Operation Finished"
},
{,
"EventCode":"0x1D144",
"EventName":"PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
@ -480,14 +440,9 @@
"BriefDescription":"XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued"
},
{,
"EventCode":"0xC094",
"EventName":"PM_LS0_UNALIGNED_LD",
"BriefDescription":"Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0xF8BC",
"EventName":"PM_LS3_UNALIGNED_ST",
"BriefDescription":"Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
"EventCode":"0x460AE",
"EventName":"PM_L3_P2_CO_RTY",
"BriefDescription":"L3 CO received retry port 2 (memory only), every retry counted"
},
{,
"EventCode":"0x58B0",
@ -504,11 +459,6 @@
"EventName":"PM_TM_ST_CONF",
"BriefDescription":"TM Store (fav or non-fav) ran into conflict (failed)"
},
{,
"EventCode":"0xD998",
"EventName":"PM_MRK_LSU_FLUSH_EMSH",
"BriefDescription":"An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address"
},
{,
"EventCode":"0xF8A0",
"EventName":"PM_NON_DATA_STORE",
@ -524,11 +474,6 @@
"EventName":"PM_BR_UNCOND",
"BriefDescription":"Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve."
},
{,
"EventCode":"0x1F056",
"EventName":"PM_RADIX_PWC_L1_HIT",
"BriefDescription":"A radix translation attempt missed in the TLB and only the first level page walk cache was a hit."
},
{,
"EventCode":"0xF8A8",
"EventName":"PM_DC_PREF_FUZZY_CONF",
@ -544,6 +489,11 @@
"EventName":"PM_LSU2_TM_L1_MISS",
"BriefDescription":"Load tm L1 miss"
},
{,
"EventCode":"0xC880",
"EventName":"PM_LS1_LD_VECTOR_FIN",
"BriefDescription":""
},
{,
"EventCode":"0x2894",
"EventName":"PM_TM_OUTER_TEND",
@ -564,21 +514,11 @@
"EventName":"PM_MRK_LSU_DERAT_MISS",
"BriefDescription":"Marked derat reload (miss) for any page size"
},
{,
"EventCode":"0x160A0",
"EventName":"PM_L3_PF_MISS_L3",
"BriefDescription":"L3 PF missed in L3"
},
{,
"EventCode":"0x1C04A",
"EventName":"PM_DATA_FROM_RL2L3_SHR",
"BriefDescription":"The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
},
{,
"EventCode":"0xD99C",
"EventName":"PM_MRK_LSU_FLUSH_UE",
"BriefDescription":"Correctable ECC error on reload data, reported at critical data forward time"
},
{,
"EventCode":"0x268B0",
"EventName":"PM_L3_P1_GRP_PUMP",
@ -629,11 +569,6 @@
"EventName":"PM_TMA_REQ_L2",
"BriefDescription":"addrs only req to L2 only on the first one,Indication that Load footprint is not expanding"
},
{,
"EventCode":"0x5884",
"EventName":"PM_DECODE_LANES_NOT_AVAIL",
"BriefDescription":"Decode has something to transmit but dispatch lanes are not available"
},
{,
"EventCode":"0x3C042",
"EventName":"PM_DATA_FROM_L3_DISP_CONFLICT",
@ -690,9 +625,9 @@
"BriefDescription":"False LHS match detected"
},
{,
"EventCode":"0xD9A4",
"EventName":"PM_MRK_LSU_FLUSH_LARX_STCX",
"BriefDescription":"A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches"
"EventCode":"0xF0B0",
"EventName":"PM_L3_LD_PREF",
"BriefDescription":"L3 load prefetch, sourced from a hardware or software stream, was sent to the nest"
},
{,
"EventCode":"0x4D012",
@ -715,9 +650,9 @@
"BriefDescription":"All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)"
},
{,
"EventCode":"0xF8B8",
"EventName":"PM_LS1_UNALIGNED_ST",
"BriefDescription":"Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
"EventCode":"0x160A0",
"EventName":"PM_L3_PF_MISS_L3",
"BriefDescription":"L3 PF missed in L3"
},
{,
"EventCode":"0x408C",
@ -764,11 +699,6 @@
"EventName":"PM_TM_NESTED_TEND",
"BriefDescription":"Completion time nested tend"
},
{,
"EventCode":"0x36084",
"EventName":"PM_L2_RCST_DISP",
"BriefDescription":"All D-side store dispatch attempts for this thread"
},
{,
"EventCode":"0x368A0",
"EventName":"PM_L3_PF_OFF_CHIP_CACHE",
@ -829,11 +759,6 @@
"EventName":"PM_L3_SN_USAGE",
"BriefDescription":"Rotating sample of 16 snoop valids"
},
{,
"EventCode":"0x16084",
"EventName":"PM_L2_RCLD_DISP",
"BriefDescription":"All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)"
},
{,
"EventCode":"0x1608C",
"EventName":"PM_RC0_BUSY",
@ -842,7 +767,7 @@
{,
"EventCode":"0x36082",
"EventName":"PM_L2_LD_DISP",
"BriefDescription":"All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)."
"BriefDescription":"All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)"
"BriefDescription":"Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0x488C",
"EventName":"PM_IC_PREF_WRITE",
@ -1017,7 +937,7 @@
{,
"EventCode":"0x3E05E",
"EventName":"PM_L3_CO_MEPF",
"BriefDescription":"L3 castouts in Mepf state for this thread"
"BriefDescription":"L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request"
},
{,
"EventCode":"0x460A2",
@ -1204,11 +1124,6 @@
"EventName":"PM_TM_FAIL_NON_TX_CONFLICT",
"BriefDescription":"Non transactional conflict from LSU, gets reported to TEXASR"
},
{,
"EventCode":"0xD198",
"EventName":"PM_MRK_LSU_FLUSH_ATOMIC",
"BriefDescription":"Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed"
},
{,
"EventCode":"0x201E0",
"EventName":"PM_MRK_DATA_FROM_MEMORY",
@ -1294,11 +1209,6 @@
"EventName":"PM_ICT_NOSLOT_DISP_HELD_HB_FULL",
"BriefDescription":"Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
},
{,
"EventCode":"0xC894",
"EventName":"PM_LS1_UNALIGNED_LD",
"BriefDescription":"Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0x360A2",
"EventName":"PM_L3_L2_CO_HIT",
@ -1324,11 +1234,6 @@
"EventName":"PM_L2_CASTOUT_SHR",
"BriefDescription":"L2 Castouts - Shared (Tx,Sx)"
},
{,
"EventCode":"0xD884",
"EventName":"PM_LSU3_SET_MPRED",
"BriefDescription":"Set prediction(set-p) miss. The entry was not found in the Set prediction table"
},
{,
"EventCode":"0x26092",
"EventName":"PM_L2_LD_MISS_64B",
@ -1362,12 +1267,12 @@
{,
"EventCode":"0xD8A8",
"EventName":"PM_ISLB_MISS",
"BriefDescription":"Instruction SLB miss - Total of all segment sizes"
"BriefDescription":"Instruction SLB Miss - Total of all segment sizes"
},
{,
"EventCode":"0xD19C",
"EventName":"PM_MRK_LSU_FLUSH_RELAUNCH_MISS",
"BriefDescription":"If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent"
"EventCode":"0x368AE",
"EventName":"PM_L3_P1_CO_RTY",
"BriefDescription":"L3 CO received retry port 1 (memory only), every retry counted"
},
{,
"EventCode":"0x260A2",
@ -1384,6 +1289,11 @@
"EventName":"PM_CMPLU_STALL_NESTED_TBEGIN",
"BriefDescription":"Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT"
},
{,
"EventCode":"0xC084",
"EventName":"PM_LS2_LD_VECTOR_FIN",
"BriefDescription":""
},
{,
"EventCode":"0x1608E",
"EventName":"PM_ST_CAUSED_FAIL",
@ -1409,11 +1319,6 @@
"EventName":"PM_CO_USAGE",
"BriefDescription":"Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running"
},
{,
"EventCode":"0xD084",
"EventName":"PM_LSU2_SET_MPRED",
"BriefDescription":"Set prediction(set-p) miss. The entry was not found in the Set prediction table"
},
{,
"EventCode":"0x48B8",
"EventName":"PM_BR_MPRED_TAKEN_TA",
@ -1449,30 +1354,25 @@
"EventName":"PM_DC_PREF_STRIDED_CONF",
"BriefDescription":"A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software."
},
{,
"EventCode":"0x36084",
"EventName":"PM_L2_RCST_DISP",
"BriefDescription":"All D-side store dispatch attempts for this thread"
"BriefDescription":"Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)"
},
{,
"EventCode":"0x201E8",
"EventName":"PM_THRESH_EXC_512",
"BriefDescription":"Threshold counter exceeded a value of 512"
},
{,
"EventCode":"0x5084",
"EventName":"PM_DECODE_FUSION_EXT_ADD",
"BriefDescription":"32-bit extended addition"
},
{,
"EventCode":"0x36080",
"EventName":"PM_L2_INST",
"BriefDescription":"All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)."
"BriefDescription":"All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)"
},
{,
"EventCode":"0x3504C",
@ -1554,21 +1454,11 @@
"EventName":"PM_MEM_RWITM",
"BriefDescription":"Memory Read With Intent to Modify for this thread"
},
{,
"EventCode":"0x26882",
"EventName":"PM_L2_DC_INV",
"BriefDescription":"D-cache invalidates sent over the reload bus to the core"
},
{,
"EventCode":"0xC090",
"EventName":"PM_LSU_STCX",
"BriefDescription":"STCX sent to nest, i.e. total"
},
{,
"EventCode":"0xD080",
"EventName":"PM_LSU0_SET_MPRED",
"BriefDescription":"Set prediction(set-p) miss. The entry was not found in the Set prediction table"
},
{,
"EventCode":"0x2C120",
"EventName":"PM_MRK_DATA_FROM_L2_NO_CONFLICT",
@ -1609,11 +1499,6 @@
"EventName":"PM_IPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription":"A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request"
},
{,
"EventCode":"0xD9A0",
"EventName":"PM_MRK_LSU_FLUSH_LHL_SHL",
"BriefDescription":"The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores)."
},
{,
"EventCode":"0x35042",
"EventName":"PM_IPTEG_FROM_L3_DISP_CONFLICT",
@ -1692,7 +1577,7 @@
{,
"EventCode":"0x2001A",
"EventName":"PM_NTC_ALL_FIN",
"BriefDescription":"Cycles after all instructions have finished to group completed"
"BriefDescription":"Cycles after instruction finished to instruction completed."
},
{,
"EventCode":"0x3005A",
@ -1709,6 +1594,11 @@
"EventName":"PM_LSU1_L1_CAM_CANCEL",
"BriefDescription":"ls1 l1 tm cam cancel"
},
{,
"EventCode":"0x268AE",
"EventName":"PM_L3_P3_PF_RTY",
"BriefDescription":"L3 PF received retry port 3, every retry counted"
},
{,
"EventCode":"0xE884",
"EventName":"PM_LS1_ERAT_MISS_PREF",
@ -1742,7 +1632,7 @@
{,
"EventCode":"0x160B6",
"EventName":"PM_L3_WI0_BUSY",
"BriefDescription":"Rotating sample of 8 WI valid"
"BriefDescription":"Rotating sample of 8 WI valid (duplicate)"
},
{,
"EventCode":"0x368AC",
@ -1790,9 +1680,9 @@
"BriefDescription":"L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)"
},
{,
"EventCode":"0x589C",
"EventName":"PM_PTESYNC",
"BriefDescription":"ptesync instruction counted when the instruction is decoded and transmitted"
"EventCode":"0x260AE",
"EventName":"PM_L3_P2_PF_RTY",
"BriefDescription":"L3 PF received retry port 2, every retry counted"
},
{,
"EventCode":"0x26086",
@ -1824,6 +1714,11 @@
"EventName":"PM_SHL_ST_DEP_CREATED",
"BriefDescription":"Store-Hit-Load Table Read Hit with entry Enabled"
},
{,
"EventCode":"0x46882",
"EventName":"PM_L2_ST_HIT",
"BriefDescription":"All successful D-side store dispatches for this thread that were L2 hits"
},
{,
"EventCode":"0x360AC",
"EventName":"PM_L3_SN0_BUSY",
@ -1844,11 +1739,6 @@
"EventName":"PM_L2_ST_MISS",
"BriefDescription":"All successful D-Side Store dispatches that were an L2 miss for this thread"
},
{,
"EventCode":"0xF8B4",
"EventName":"PM_DC_PREF_XCONS_ALLOC",
"BriefDescription":"Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch"
},
{,
"EventCode":"0x35048",
"EventName":"PM_IPTEG_FROM_DL2L3_SHR",
@ -1969,11 +1859,6 @@
"EventName":"PM_THRD_PRIO_2_3_CYC",
"BriefDescription":"Cycles thread running at priority level 2 or 3"
},
{,
"EventCode":"0x10134",
"EventName":"PM_MRK_ST_DONE_L2",
"BriefDescription":"marked store completed in L2 ( RC machine done)"
},
{,
"EventCode":"0x368B2",
"EventName":"PM_L3_GRP_GUESS_WRONG_HIGH",
@ -2004,11 +1889,6 @@
"EventName":"PM_L2_GRP_GUESS_WRONG",
"BriefDescription":"L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)"
},
{,
"EventCode":"0x368AE",
"EventName":"PM_L3_P1_CO_RTY",
"BriefDescription":"L3 CO received retry port 1 (memory only), every retry counted"
},
{,
"EventCode":"0xC0AC",
"EventName":"PM_LSU_FLUSH_EMSH",
@ -2034,11 +1914,6 @@
"EventName":"PM_L2_GROUP_PUMP",
"BriefDescription":"RC requests that were on group (aka nodel) pump attempts"
},
{,
"EventCode":"0xF0B0",
"EventName":"PM_L3_LD_PREF",
"BriefDescription":"L3 load prefetch, sourced from a hardware or software stream, was sent to the nest"
"BriefDescription":"Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time"
},
{,
"EventCode":"0xF0B8",
"EventName":"PM_LS0_UNALIGNED_ST",
"BriefDescription":"Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode":"0x20132",
"EventName":"PM_MRK_DFU_FIN",
@ -2139,6 +2014,11 @@
"EventName":"PM_LSU_FLUSH_LHS",
"BriefDescription":"Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed"
},
{,
"EventCode":"0x16084",
"EventName":"PM_L2_RCLD_DISP",
"BriefDescription":"All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)"
},
{,
"EventCode":"0x3F150",
"EventName":"PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
@ -2224,11 +2104,6 @@
"EventName":"PM_IC_PREF_CANCEL_PAGE",
"BriefDescription":"Prefetch Canceled due to page boundary"
},
{,
"EventCode":"0xF09C",
"EventName":"PM_SLB_TABLEWALK_CYC",
"BriefDescription":"Cycles when a tablewalk is pending on this thread on the SLB table"
},
{,
"EventCode":"0x460AA",
"EventName":"PM_L3_P0_CO_L31",
@ -2247,10 +2122,10 @@
{,
"EventCode":"0x46082",
"EventName":"PM_L2_ST_DISP",
"BriefDescription":"All successful D-side store dispatches for this thread "
"BriefDescription":"All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
},
{,
"EventCode":"0x4609E",
"EventCode":"0x36880",
"EventName":"PM_L2_INST_MISS",
"BriefDescription":"All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)"
},
@ -2340,9 +2215,9 @@
"BriefDescription":"All ISU rejects"
},
{,
"EventCode":"0x46882",
"EventName":"PM_L2_ST_HIT",
"BriefDescription":"All successful D-side store dispatches for this thread that were L2 hits"
"EventCode":"0xC884",
"EventName":"PM_LS3_LD_VECTOR_FIN",
"BriefDescription":""
},
{,
"EventCode":"0x360A8",
@ -2359,11 +2234,6 @@
"EventName":"PM_LSU_NCST",
"BriefDescription":"Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1"
},
{,
"EventCode":"0xD880",
"EventName":"PM_LSU1_SET_MPRED",
"BriefDescription":"Set prediction(set-p) miss. The entry was not found in the Set prediction table"
},
{,
"EventCode":"0xD0B8",
"EventName":"PM_LSU_LMQ_FULL_CYC",
@ -2389,4 +2259,4 @@
"EventName":"PM_L3_PF_USAGE",
"BriefDescription":"Rotating sample of 32 PF actives"
"BriefDescription":"Floating Point Operation Finished"
},
{,
"EventCode":"0x2C018",
"EventName":"PM_CMPLU_STALL_DMISS_L21_L31",
@ -389,11 +394,6 @@
"EventName":"PM_ICT_NOSLOT_BR_MPRED",
"BriefDescription":"Ict empty for this thread due to branch mispred"
},
{,
"EventCode":"0x3405E",
"EventName":"PM_IFETCH_THROTTLE",
"BriefDescription":"Cycles in which Instruction fetch throttle was active."
},
{,
"EventCode":"0x1F148",
"EventName":"PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
@ -422,7 +422,7 @@
{,
"EventCode":"0xD0A8",
"EventName":"PM_DSLB_MISS",
"BriefDescription":"Data SLB Miss - Total of all segment sizes"
"BriefDescription":"gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))"
},
{,
"EventCode":"0x4C058",
@ -549,4 +549,4 @@
"EventName":"PM_MRK_DATA_FROM_L21_SHR_CYC",
"BriefDescription":"Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load"
Sukadev Bhattiprolu