mirror of https://gitee.com/openkylin/linux.git
powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx
Adds a register to the config space for the 460sx. Changes the vc0 detect to a pll detect. maps configuration space to test the link status. changes the setup to enable gen2 devices to operate at gen2 speeds. fixes mapping that was not correct for the 460sx. added bit definitions for the OMRxMSKL registers. Removed reserved bit that was set incorrectly in the OMR2MSKL register. tested on the 460sx eiger and custom board Signed-off-by: Ayman El-Khashab <ayman@elkhashab.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
This commit is contained in:
Ayman El-Khashab
Josh Boyer
parent
2f6bab96ef
commit
e7fa1d1314
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@ -1091,6 +1091,10 @@ static int __init ppc460sx_pciex_core_init(struct device_node *np)
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mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
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mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
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/* Set HSS PRBS enabled */
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mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
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mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
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udelay(100);
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/* De-assert PLLRESET */
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@ -1131,9 +1135,6 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
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0, 0x01000000);
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/*Gen-1*/
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mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
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(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
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PESDRx_RCSSET_RSTPYN);
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@ -1147,14 +1148,42 @@ static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
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{
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/* Max 128 Bytes */
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out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
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/* Assert VRB and TXE - per datasheet turn off addr validation */
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out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
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return 0;
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}
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static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
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{
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void __iomem *mbase;
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int attempt = 50;
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port->link = 0;
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mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
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if (mbase == NULL) {
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printk(KERN_ERR "%s: Can't map internal config space !",
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port->node->full_name);
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goto done;
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}
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while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
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& PECFG_460SX_DLLSTA_LINKUP))) {
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attempt--;
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mdelay(10);
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}
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if (attempt)
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port->link = 1;
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done:
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iounmap(mbase);
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}
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static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
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.core_init = ppc460sx_pciex_core_init,
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.port_init_hw = ppc460sx_pciex_init_port_hw,
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.setup_utl = ppc460sx_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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.check_link = ppc460sx_pciex_check_link,
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};
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#endif /* CONFIG_44x */
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@ -1337,15 +1366,15 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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if (rc != 0)
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return rc;
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if (ppc4xx_pciex_hwops->check_link)
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ppc4xx_pciex_hwops->check_link(port);
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/*
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* Initialize mapping: disable all regions and configure
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* CFG and REG regions based on resources in the device tree
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*/
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ppc4xx_pciex_port_init_mapping(port);
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if (ppc4xx_pciex_hwops->check_link)
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ppc4xx_pciex_hwops->check_link(port);
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/*
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* Map UTL
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*/
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@ -1359,13 +1388,23 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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ppc4xx_pciex_hwops->setup_utl(port);
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/*
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* Check for VC0 active and assert RDY.
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* Check for VC0 active or PLL Locked and assert RDY.
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*/
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if (port->sdr_base) {
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if (port->link &&
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if (of_device_is_compatible(port->node,
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"ibm,plb-pciex-460sx")){
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if (port->link && ppc4xx_pciex_wait_on_sdr(port,
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PESDRn_RCSSTS,
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1 << 12, 1 << 12, 5000)) {
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printk(KERN_INFO "PCIE%d: PLL not locked\n",
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port->index);
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port->link = 0;
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}
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} else if (port->link &&
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ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
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1 << 16, 1 << 16, 5000)) {
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printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
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printk(KERN_INFO "PCIE%d: VC0 not active\n",
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port->index);
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port->link = 0;
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}
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@ -1572,8 +1611,15 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
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/* Note that 3 here means enabled | single region */
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
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/*Enabled and single region */
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if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
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sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
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| DCRO_PEGPL_OMRxMSKL_VAL);
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else
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dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
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sa | DCRO_PEGPL_OMR1MSKL_UOT
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| DCRO_PEGPL_OMRxMSKL_VAL);
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break;
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case 1:
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out_le32(mbase + PECFG_POM1LAH, pciah);
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@ -1581,8 +1627,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
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dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
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/* Note that 3 here means enabled | single region */
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dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
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sa | DCRO_PEGPL_OMRxMSKL_VAL);
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break;
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case 2:
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out_le32(mbase + PECFG_POM2LAH, pciah);
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@ -1591,7 +1637,9 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
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dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
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/* Note that 3 here means enabled | IO space !!! */
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dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3);
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dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
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sa | DCRO_PEGPL_OMR3MSKL_IO
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| DCRO_PEGPL_OMRxMSKL_VAL);
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break;
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}
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@ -1692,6 +1740,9 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
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if (res->flags & IORESOURCE_PREFETCH)
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sa |= 0x8;
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if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
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sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
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out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
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out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
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@ -1853,6 +1904,10 @@ static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
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}
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out_le16(mbase + 0x202, val);
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/* Enable Bus master, memory, and io space */
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if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
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out_le16(mbase + 0x204, 0x7);
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if (!port->endpoint) {
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/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
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out_le32(mbase + 0x208, 0x06040001);
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@ -464,6 +464,18 @@
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#define PECFG_POM2LAL 0x390
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#define PECFG_POM2LAH 0x394
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/* 460sx only */
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#define PECFG_460SX_DLLSTA 0x3f8
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/* 460sx Bit Mappings */
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#define PECFG_460SX_DLLSTA_LINKUP 0x00000010
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#define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004
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/* PEGPL Bit Mappings */
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#define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001
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#define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002
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#define DCRO_PEGPL_OMR3MSKL_IO 0x00000002
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/* SDR Bit Mappings */
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#define PESDRx_RCSSET_HLDPLB 0x10000000
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#define PESDRx_RCSSET_RSTGU 0x01000000
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