mirror of https://gitee.com/openkylin/linux.git
tg3: Add new HW_TSO_3 flag for 5717
The 5717 sets up TSO slightly differently in the transmit path. It looks like this method will be the new way of doing things. This patch defines a flag to indicate this. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
507399f18e
commit
e849cdc309
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@ -5206,7 +5206,7 @@ static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
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}
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/* hard_start_xmit for devices that don't have any bugs and
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* support TG3_FLG2_HW_TSO_2 only.
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* support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
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*/
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static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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struct net_device *dev)
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@ -5265,7 +5265,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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hdrlen = ip_tcp_len + tcp_opt_len;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
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mss |= (hdrlen & 0xc) << 12;
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if (hdrlen & 0x10)
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base_flags |= 0x00000010;
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@ -7523,7 +7523,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
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@ -9513,15 +9514,16 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
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return 0;
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}
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if ((dev->features & NETIF_F_IPV6_CSUM) &&
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(tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
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((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
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(tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
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if (value) {
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dev->features |= NETIF_F_TSO6;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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dev->features |= NETIF_F_TSO_ECN;
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} else
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dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
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@ -12670,8 +12672,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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}
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/* Determine TSO capabilities */
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if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
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else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
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@ -14136,22 +14140,23 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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* Firmware TSO on older chips gives lower performance, so it
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* is off by default, but can be enabled using ethtool.
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*/
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
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if (dev->features & NETIF_F_IP_CSUM)
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dev->features |= NETIF_F_TSO;
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if ((dev->features & NETIF_F_IPV6_CSUM) &&
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(tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
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if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
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(dev->features & NETIF_F_IP_CSUM))
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dev->features |= NETIF_F_TSO;
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if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
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(tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
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if (dev->features & NETIF_F_IPV6_CSUM)
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dev->features |= NETIF_F_TSO6;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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dev->features |= NETIF_F_TSO_ECN;
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}
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
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!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
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!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
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@ -2753,6 +2753,7 @@ struct tg3 {
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#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
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#define TG3_FLG2_5705_PLUS 0x00040000
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#define TG3_FLG2_5750_PLUS 0x00080000
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#define TG3_FLG2_HW_TSO_3 0x00100000
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#define TG3_FLG2_USING_MSI 0x00200000
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#define TG3_FLG2_USING_MSIX 0x00400000
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#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
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@ -2764,7 +2765,9 @@ struct tg3 {
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#define TG3_FLG2_ICH_WORKAROUND 0x02000000
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#define TG3_FLG2_5780_CLASS 0x04000000
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#define TG3_FLG2_HW_TSO_2 0x08000000
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
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TG3_FLG2_HW_TSO_2 | \
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TG3_FLG2_HW_TSO_3)
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
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#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
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