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drm/gf100-/gr: remove some broken ltc bashing, for now 

... and hope that the defaults are good enough.  This was always
supposed to be a read/modify/write thing anyway, so we're writing
very wrong stuff for some boards already.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-08-10 04:10:30 +10:00
parent 67cfbfdfec
commit e887377338
13 changed files with 0 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
View File

@ -82,7 +82,6 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nve4_grctx_generate_main, .main = nve4_grctx_generate_main,
.mods = nve4_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nvf0_grctx_pack_hub, .hub = nvf0_grctx_pack_hub,
.gpc = nvf0_grctx_pack_gpc, .gpc = nvf0_grctx_pack_gpc,

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
View File

@ -41,7 +41,6 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nve4_grctx_generate_main, .main = nve4_grctx_generate_main,
.mods = nve4_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nve4_grctx_pack_hub, .hub = nve4_grctx_pack_hub,
.gpc = nve4_grctx_pack_gpc, .gpc = nve4_grctx_pack_gpc,

7
drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
View File

@ -929,11 +929,6 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info)
} }
} }
void
gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
}
static void static void
gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
{ {
@ -971,7 +966,6 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
oclass->bundle(info); oclass->bundle(info);
oclass->pagepool(info); oclass->pagepool(info);
oclass->attrib(info); oclass->attrib(info);
oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
gm107_grctx_generate_tpcid(priv); gm107_grctx_generate_tpcid(priv);
@ -1016,7 +1010,6 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = gm107_grctx_generate_main, .main = gm107_grctx_generate_main,
.mods = gm107_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = gm107_grctx_pack_hub, .hub = gm107_grctx_pack_hub,
.gpc = gm107_grctx_pack_gpc, .gpc = gm107_grctx_pack_gpc,

8
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
View File

@ -531,13 +531,6 @@ nv108_grctx_pack_ppc[] = {
* PGRAPH context implementation * PGRAPH context implementation
******************************************************************************/ ******************************************************************************/
static void
nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
mmio_list(0x17e91c, 0x0b040a0b, 0, 0);
mmio_list(0x17e920, 0x00090d08, 0, 0);
}
struct nouveau_oclass * struct nouveau_oclass *
nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08), .base.handle = NV_ENGCTX(GR, 0x08),
@ -550,7 +543,6 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nve4_grctx_generate_main, .main = nve4_grctx_generate_main,
.mods = nv108_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nv108_grctx_pack_hub, .hub = nv108_grctx_pack_hub,
.gpc = nv108_grctx_pack_gpc, .gpc = nv108_grctx_pack_gpc,

7
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View File

@ -1073,11 +1073,6 @@ nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
} }
} }
void
nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
}
void void
nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
{ {
@ -1247,7 +1242,6 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
oclass->bundle(info); oclass->bundle(info);
oclass->pagepool(info); oclass->pagepool(info);
oclass->attrib(info); oclass->attrib(info);
oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
nvc0_grctx_generate_tpcid(priv); nvc0_grctx_generate_tpcid(priv);
@ -1375,7 +1369,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvc0_grctx_generate_main, .main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn, .unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub, .hub = nvc0_grctx_pack_hub,
.gpc = nvc0_grctx_pack_gpc, .gpc = nvc0_grctx_pack_gpc,

7
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
View File

@ -15,9 +15,6 @@ struct nvc0_grctx {
int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access); int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int); void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
#define mmio_data(a,b,c) nvc0_grctx_mmio_data(info, (a), (b), (c))
#define mmio_list(a,b,c,d) nvc0_grctx_mmio_item(info, (a), (b), (c), (d))
#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d)) #define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e)) #define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) #define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
@ -28,7 +25,6 @@ struct nvc0_grctx_oclass {
/* main context generation function */ /* main context generation function */
void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *); void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
/* context-specific modify-on-first-load list generation function */ /* context-specific modify-on-first-load list generation function */
void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
void (*unkn)(struct nvc0_graph_priv *); void (*unkn)(struct nvc0_graph_priv *);
/* mmio context data */ /* mmio context data */
const struct nvc0_graph_pack *hub; const struct nvc0_graph_pack *hub;
@ -67,7 +63,6 @@ void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_bundle(struct nvc0_grctx *); void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
void nvc0_grctx_generate_pagepool(struct nvc0_grctx *); void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
void nvc0_grctx_generate_attrib(struct nvc0_grctx *); void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *); void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
@ -77,7 +72,6 @@ void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc1_grctx_oclass; extern struct nouveau_oclass *nvc1_grctx_oclass;
void nvc1_grctx_generate_attrib(struct nvc0_grctx *); void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc4_grctx_oclass; extern struct nouveau_oclass *nvc4_grctx_oclass;
@ -93,7 +87,6 @@ extern struct nouveau_oclass *gk20a_grctx_oclass;
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_bundle(struct nvc0_grctx *); void nve4_grctx_generate_bundle(struct nvc0_grctx *);
void nve4_grctx_generate_pagepool(struct nvc0_grctx *); void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);

6
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View File

@ -763,11 +763,6 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
} }
} }
void
nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
}
void void
nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
{ {
@ -791,7 +786,6 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvc0_grctx_generate_main, .main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn, .unkn = nvc1_grctx_generate_unkn,
.hub = nvc1_grctx_pack_hub, .hub = nvc1_grctx_pack_hub,
.gpc = nvc1_grctx_pack_gpc, .gpc = nvc1_grctx_pack_gpc,

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
View File

@ -92,7 +92,6 @@ nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvc0_grctx_generate_main, .main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn, .unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub, .hub = nvc0_grctx_pack_hub,
.gpc = nvc0_grctx_pack_gpc, .gpc = nvc0_grctx_pack_gpc,

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
View File

@ -343,7 +343,6 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvc0_grctx_generate_main, .main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn, .unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub, .hub = nvc0_grctx_pack_hub,
.gpc = nvc8_grctx_pack_gpc, .gpc = nvc8_grctx_pack_gpc,

8
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View File

@ -214,12 +214,6 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
} }
} }
static void
nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
}
void void
nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{ {
@ -239,7 +233,6 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
oclass->bundle(info); oclass->bundle(info);
oclass->pagepool(info); oclass->pagepool(info);
oclass->attrib(info); oclass->attrib(info);
oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
nvc0_grctx_generate_tpcid(priv); nvc0_grctx_generate_tpcid(priv);
@ -269,7 +262,6 @@ nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvd7_grctx_generate_main, .main = nvd7_grctx_generate_main,
.mods = nvd7_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nvd7_grctx_pack_hub, .hub = nvd7_grctx_pack_hub,
.gpc = nvd7_grctx_pack_gpc, .gpc = nvd7_grctx_pack_gpc,

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View File

@ -511,7 +511,6 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nvc0_grctx_generate_main, .main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn, .unkn = nvc1_grctx_generate_unkn,
.hub = nvd9_grctx_pack_hub, .hub = nvd9_grctx_pack_hub,
.gpc = nvd9_grctx_pack_gpc, .gpc = nvd9_grctx_pack_gpc,

9
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
View File

@ -869,13 +869,6 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
mmio_wr32(info, 0x4064cc, 0x80000000); mmio_wr32(info, 0x4064cc, 0x80000000);
} }
void
nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
mmio_list(0x17e91c, 0x06060609, 0, 0);
mmio_list(0x17e920, 0x00090a05, 0, 0);
}
void void
nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
{ {
@ -964,7 +957,6 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
oclass->bundle(info); oclass->bundle(info);
oclass->pagepool(info); oclass->pagepool(info);
oclass->attrib(info); oclass->attrib(info);
oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
nvc0_grctx_generate_tpcid(priv); nvc0_grctx_generate_tpcid(priv);
@ -1006,7 +998,6 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nve4_grctx_generate_main, .main = nve4_grctx_generate_main,
.mods = nve4_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nve4_grctx_pack_hub, .hub = nve4_grctx_pack_hub,
.gpc = nve4_grctx_pack_gpc, .gpc = nve4_grctx_pack_gpc,

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
View File

@ -821,7 +821,6 @@ nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.wr32 = _nouveau_graph_context_wr32, .wr32 = _nouveau_graph_context_wr32,
}, },
.main = nve4_grctx_generate_main, .main = nve4_grctx_generate_main,
.mods = nve4_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn, .unkn = nve4_grctx_generate_unkn,
.hub = nvf0_grctx_pack_hub, .hub = nvf0_grctx_pack_hub,
.gpc = nvf0_grctx_pack_gpc, .gpc = nvf0_grctx_pack_gpc,