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clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() 

The .set_rate() callback for the SD clocks is always called with a valid
clock rate, returned by .round_rate().  Hence there is no need to
iterate through the divider table twice: once to repeat the work done by
.round_rate(), and a second time to find the corresponding divider
entry.

Just iterate once, looking for the divider that matches the passed clock
rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2019-08-30 15:45:10 +02:00
parent b5dea62d34
commit e8adb3a0f7
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/renesas/rcar-gen3-cpg.c
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@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
} }
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate) unsigned long parent_rate)
{ {
struct sd_clock *clock = to_sd_clock(hw); struct sd_clock *clock = to_sd_clock(hw);
unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
unsigned int i; unsigned int i;
for (i = 0; i < clock->div_num; i++) for (i = 0; i < clock->div_num; i++)
if (div == clock->div_table[i].div) if (rate == DIV_ROUND_CLOSEST(parent_rate,
clock->div_table[i].div))
break; break;
if (i >= clock->div_num) if (i >= clock->div_num)