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ARM: 8707/1: NOMMU: Update MPU accessors to use cp15 helpers 

Currently, inline assembly for accessing to MPU's cp15 lacks volatile
keyword which opens possibility to compiler to optimise such accesses
as soon as we start using them more intensively. Rather than fixing
inline asm, lets move MPU accessors to use cp15 helpers which do the
right thing.

Tested-by: Szemző András <sza@esh.hu>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin 2017-10-16 12:53:18 +01:00 committed by Russell King
parent 877ec119db
commit e8b47e12d6
1 changed files with 26 additions and 22 deletions
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48
arch/arm/mm/pmsa-v7.c
View File

@ -12,63 +12,67 @@
#include "mm.h"
#define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
#define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
#define DRSR __ACCESS_CP15(c6, 0, c1, 2)
#define IRSR __ACCESS_CP15(c6, 0, c1, 3)
#define DRACR __ACCESS_CP15(c6, 0, c1, 4)
#define IRACR __ACCESS_CP15(c6, 0, c1, 5)
#define RNGNR __ACCESS_CP15(c6, 0, c2, 0)
/* Region number */
static void rgnr_write(u32 v)
static inline void rgnr_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
write_sysreg(v, RNGNR);
}
/* Data-side / unified region attributes */
/* Region access control register */
static void dracr_write(u32 v)
static inline void dracr_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
write_sysreg(v, DRACR);
}
/* Region size register */
static void drsr_write(u32 v)
static inline void drsr_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
write_sysreg(v, DRSR);
}
/* Region base address register */
static void drbar_write(u32 v)
static inline void drbar_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
write_sysreg(v, DRBAR);
}
static u32 drbar_read(void)
static inline u32 drbar_read(void)
{
u32 v;
asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
return v;
return read_sysreg(DRBAR);
}
/* Optional instruction-side region attributes */
/* I-side Region access control register */
static void iracr_write(u32 v)
static inline void iracr_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
write_sysreg(v, IRACR);
}
/* I-side Region size register */
static void irsr_write(u32 v)
static inline void irsr_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
write_sysreg(v, IRSR);
}
/* I-side Region base address register */
static void irbar_write(u32 v)
static inline void irbar_write(u32 v)
{
asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
write_sysreg(v, IRBAR);
}
static unsigned long irbar_read(void)
static inline u32 irbar_read(void)
{
unsigned long v;
asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
return v;
return read_sysreg(IRBAR);
}
/* MPU initialisation functions */