mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: Fix async fifo for AR9287
Async fifo is now enabled only for versions 1.3 and above. Enable it in the appropriate place, in the reset routine, instead of process_ini(). Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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15ae733b25
commit
e9141f71f4
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@ -742,17 +742,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
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return -EINVAL;
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}
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if (AR_SREV_9287_12_OR_LATER(ah)) {
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/* Enable ASYNC FIFO */
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
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REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
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REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
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}
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/*
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* Set correct baseband to analog shift setting to
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* access analog chips.
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@ -18,6 +18,7 @@
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#include "ar5008_initvals.h"
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#include "ar9001_initvals.h"
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#include "ar9002_initvals.h"
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#include "ar9002_phy.h"
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/* General hardware code for the A5008/AR9001/AR9002 hadware families */
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@ -565,18 +566,29 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
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return 0;
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}
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void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
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{
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if (AR_SREV_9287_13_OR_LATER(ah)) {
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
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REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
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REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
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}
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}
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/*
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* Enable ASYNC FIFO
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*
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* If Async FIFO is enabled, the following counters change as MAC now runs
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* at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
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*
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* The values below tested for ht40 2 chain.
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* Overwrite the delay/timeouts initialized in process ini.
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*/
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void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
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void ar9002_hw_update_async_fifo(struct ath_hw *ah)
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{
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if (AR_SREV_9287_12_OR_LATER(ah)) {
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if (AR_SREV_9287_13_OR_LATER(ah)) {
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REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
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AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
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REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
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@ -600,9 +612,9 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
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*/
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void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
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{
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if (AR_SREV_9287_12_OR_LATER(ah)) {
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if (AR_SREV_9287_13_OR_LATER(ah)) {
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REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
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AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
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AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
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}
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}
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@ -1298,6 +1298,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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if (AR_SREV_9280_10_OR_LATER(ah))
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
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if (!AR_SREV_9300_20_OR_LATER(ah))
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ar9002_hw_enable_async_fifo(ah);
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r = ath9k_hw_process_ini(ah, chan);
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if (r)
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return r;
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@ -1370,7 +1373,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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ath9k_hw_init_global_settings(ah);
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if (!AR_SREV_9300_20_OR_LATER(ah)) {
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ar9002_hw_enable_async_fifo(ah);
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ar9002_hw_update_async_fifo(ah);
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ar9002_hw_enable_wep_aggregation(ah);
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}
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@ -911,6 +911,7 @@ void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
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void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
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int ar9002_hw_rf_claim(struct ath_hw *ah);
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void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
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void ar9002_hw_update_async_fifo(struct ath_hw *ah);
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void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
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/*
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@ -760,32 +760,33 @@
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#define AR_SREV_REVISION2 0x00000F00
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#define AR_SREV_REVISION2_S 8
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#define AR_SREV_VERSION_5416_PCI 0xD
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#define AR_SREV_VERSION_5416_PCIE 0xC
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#define AR_SREV_REVISION_5416_10 0
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#define AR_SREV_REVISION_5416_20 1
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#define AR_SREV_REVISION_5416_22 2
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#define AR_SREV_VERSION_9100 0x14
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#define AR_SREV_VERSION_9160 0x40
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#define AR_SREV_REVISION_9160_10 0
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#define AR_SREV_REVISION_9160_11 1
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#define AR_SREV_VERSION_9280 0x80
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#define AR_SREV_REVISION_9280_10 0
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#define AR_SREV_REVISION_9280_20 1
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#define AR_SREV_REVISION_9280_21 2
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#define AR_SREV_VERSION_9285 0xC0
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#define AR_SREV_REVISION_9285_10 0
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#define AR_SREV_REVISION_9285_11 1
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#define AR_SREV_REVISION_9285_12 2
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#define AR_SREV_VERSION_9287 0x180
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#define AR_SREV_REVISION_9287_10 0
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#define AR_SREV_REVISION_9287_11 1
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#define AR_SREV_REVISION_9287_12 2
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#define AR_SREV_VERSION_9271 0x140
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#define AR_SREV_REVISION_9271_10 0
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#define AR_SREV_REVISION_9271_11 1
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#define AR_SREV_VERSION_9300 0x1c0
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#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
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#define AR_SREV_VERSION_5416_PCI 0xD
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#define AR_SREV_VERSION_5416_PCIE 0xC
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#define AR_SREV_REVISION_5416_10 0
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#define AR_SREV_REVISION_5416_20 1
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#define AR_SREV_REVISION_5416_22 2
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#define AR_SREV_VERSION_9100 0x14
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#define AR_SREV_VERSION_9160 0x40
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#define AR_SREV_REVISION_9160_10 0
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#define AR_SREV_REVISION_9160_11 1
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#define AR_SREV_VERSION_9280 0x80
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#define AR_SREV_REVISION_9280_10 0
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#define AR_SREV_REVISION_9280_20 1
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#define AR_SREV_REVISION_9280_21 2
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#define AR_SREV_VERSION_9285 0xC0
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#define AR_SREV_REVISION_9285_10 0
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#define AR_SREV_REVISION_9285_11 1
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#define AR_SREV_REVISION_9285_12 2
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#define AR_SREV_VERSION_9287 0x180
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#define AR_SREV_REVISION_9287_10 0
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#define AR_SREV_REVISION_9287_11 1
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#define AR_SREV_REVISION_9287_12 2
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#define AR_SREV_REVISION_9287_13 3
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#define AR_SREV_VERSION_9271 0x140
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#define AR_SREV_REVISION_9271_10 0
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#define AR_SREV_REVISION_9271_11 1
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#define AR_SREV_VERSION_9300 0x1c0
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#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
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#define AR_SREV_5416(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
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@ -863,6 +864,11 @@
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(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))
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#define AR_SREV_9287_13_OR_LATER(_ah) \
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(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))
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#define AR_SREV_9271(_ah) \
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(((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)
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#define AR_SREV_9271_10(_ah) \
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