mirror of https://gitee.com/openkylin/linux.git
Merge 3.17-rc3 into staging-next
We want the staging bugfixes in this branch as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
commit
e9723bf2ad
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@ -4,11 +4,13 @@ Specifying interrupt information for devices
|
|||
1) Interrupt client nodes
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-------------------------
|
||||
|
||||
Nodes that describe devices which generate interrupts must contain an either an
|
||||
"interrupts" property or an "interrupts-extended" property. These properties
|
||||
contain a list of interrupt specifiers, one per output interrupt. The format of
|
||||
the interrupt specifier is determined by the interrupt controller to which the
|
||||
interrupts are routed; see section 2 below for details.
|
||||
Nodes that describe devices which generate interrupts must contain an
|
||||
"interrupts" property, an "interrupts-extended" property, or both. If both are
|
||||
present, the latter should take precedence; the former may be provided simply
|
||||
for compatibility with software that does not recognize the latter. These
|
||||
properties contain a list of interrupt specifiers, one per output interrupt. The
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format of the interrupt specifier is determined by the interrupt controller to
|
||||
which the interrupts are routed; see section 2 below for details.
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||||
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Example:
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interrupt-parent = <&intc1>;
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|
|
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|
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@ -0,0 +1,107 @@
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* Toshiba TC3589x multi-purpose expander
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The Toshiba TC3589x series are I2C-based MFD devices which may expose the
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following built-in devices: gpio, keypad, rotator (vibrator), PWM (for
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e.g. LEDs or vibrators) The included models are:
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- TC35890
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- TC35892
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- TC35893
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- TC35894
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- TC35895
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- TC35896
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Required properties:
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- compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
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"toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896"
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- reg : I2C address of the device
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- interrupt-parent : specifies which IRQ controller we're connected to
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- interrupts : the interrupt on the parent the controller is connected to
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- interrupt-controller : marks the device node as an interrupt controller
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- #interrupt-cells : should be <1>, the first cell is the IRQ offset on this
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TC3589x interrupt controller.
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Optional nodes:
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- GPIO
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This GPIO module inside the TC3589x has 24 (TC35890, TC35892) or 20
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(other models) GPIO lines.
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- compatible : must be "toshiba,tc3589x-gpio"
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- interrupts : interrupt on the parent, which must be the tc3589x MFD device
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- interrupt-controller : marks the device node as an interrupt controller
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- #interrupt-cells : should be <2>, the first cell is the IRQ offset on this
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TC3589x GPIO interrupt controller, the second cell is the interrupt flags
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in accordance with <dt-bindings/interrupt-controller/irq.h>. The following
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flags are valid:
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- IRQ_TYPE_LEVEL_LOW
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- IRQ_TYPE_LEVEL_HIGH
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- IRQ_TYPE_EDGE_RISING
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- IRQ_TYPE_EDGE_FALLING
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- IRQ_TYPE_EDGE_BOTH
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- gpio-controller : marks the device node as a GPIO controller
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- #gpio-cells : should be <2>, the first cell is the GPIO offset on this
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GPIO controller, the second cell is the flags.
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- Keypad
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This keypad is the same on all variants, supporting up to 96 different
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keys. The linux-specific properties are modeled on those already existing
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in other input drivers.
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- compatible : must be "toshiba,tc3589x-keypad"
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- debounce-delay-ms : debounce interval in milliseconds
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- keypad,num-rows : number of rows in the matrix, see
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bindings/input/matrix-keymap.txt
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- keypad,num-columns : number of columns in the matrix, see
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bindings/input/matrix-keymap.txt
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- linux,keymap: the definition can be found in
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bindings/input/matrix-keymap.txt
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- linux,no-autorepeat: do no enable autorepeat feature.
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- linux,wakeup: use any event on keypad as wakeup event.
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Example:
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tc35893@44 {
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compatible = "toshiba,tc35893";
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reg = <0x44>;
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interrupt-parent = <&gpio6>;
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interrupts = <26 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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tc3589x_gpio {
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compatible = "toshiba,tc3589x-gpio";
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interrupts = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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tc3589x_keypad {
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compatible = "toshiba,tc3589x-keypad";
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interrupts = <6>;
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debounce-delay-ms = <4>;
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keypad,num-columns = <8>;
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keypad,num-rows = <8>;
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linux,no-autorepeat;
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linux,wakeup;
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linux,keymap = <0x0301006b
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0x04010066
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0x06040072
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0x040200d7
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0x0303006a
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0x0205000e
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0x0607008b
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0x0500001c
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0x0403000b
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0x03040034
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0x05020067
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0x0305006c
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0x040500e7
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0x0005009e
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0x06020073
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0x01030039
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0x07060069
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0x050500d9>;
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};
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};
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@ -22,7 +22,7 @@ Optional properties:
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width of 8 is assumed.
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- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
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"sw" <deprecated> use "ham1" instead
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"sw" 1-bit Hamming ecc code via software
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"hw" <deprecated> use "ham1" instead
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"hw-romcode" <deprecated> use "ham1" instead
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"ham1" 1-bit Hamming ecc code
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|
|
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@ -2,6 +2,10 @@
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
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- reg: Should contain the configuration address space.
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- reg-names: Must be "config" for the PCIe configuration space.
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(The old way of getting the configuration address space from "ranges"
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is deprecated and should be avoided.)
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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|
|
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@ -0,0 +1,59 @@
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TI PCI Controllers
|
||||
|
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PCIe Designware Controller
|
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- compatible: Should be "ti,dra7-pcie""
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- reg : Two register ranges as listed in the reg-names property
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- reg-names : The first entry must be "ti-conf" for the TI specific registers
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The second entry must be "rc-dbics" for the designware pcie
|
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registers
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The third entry must be "config" for the PCIe configuration space
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- phys : list of PHY specifiers (used by generic PHY framework)
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- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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where <X> is the instance number of the pcie from the HW spec.
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- interrupts : Two interrupt entries must be specified. The first one is for
|
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main interrupt line and the second for MSI interrupt line.
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- #address-cells,
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#size-cells,
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#interrupt-cells,
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device_type,
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ranges,
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num-lanes,
|
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interrupt-map-mask,
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interrupt-map : as specified in ../designware-pcie.txt
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Example:
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axi {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51000000 0x51000000 0x3000
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0x0 0x20000000 0x10000000>;
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pcie@51000000 {
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compatible = "ti,dra7-pcie";
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 232 0x4>, <0 233 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x20013000 0x13000 0 0xffed000>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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@ -62,7 +62,7 @@ Example:
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|||
#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 32 0x4>;
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interrupts = <0 16 0x4>;
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pinctrl-names = "default";
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pinctrl-0 = <&gsbi5_uart_default>;
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|
|
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|
|
@ -56,10 +56,10 @@ The dma_buf buffer sharing API usage contains the following steps:
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size_t size, int flags,
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const char *exp_name)
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|
||||
If this succeeds, dma_buf_export allocates a dma_buf structure, and returns a
|
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pointer to the same. It also associates an anonymous file with this buffer,
|
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so it can be exported. On failure to allocate the dma_buf object, it returns
|
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NULL.
|
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If this succeeds, dma_buf_export_named allocates a dma_buf structure, and
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returns a pointer to the same. It also associates an anonymous file with this
|
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buffer, so it can be exported. On failure to allocate the dma_buf object,
|
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it returns NULL.
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|
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'exp_name' is the name of exporter - to facilitate information while
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debugging.
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|
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@ -76,7 +76,7 @@ The dma_buf buffer sharing API usage contains the following steps:
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|||
drivers and/or processes.
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Interface:
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int dma_buf_fd(struct dma_buf *dmabuf)
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int dma_buf_fd(struct dma_buf *dmabuf, int flags)
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|
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This API installs an fd for the anonymous file associated with this buffer;
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returns either 'fd', or error.
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@ -157,7 +157,9 @@ to request use of buffer for allocation.
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"dma_buf->ops->" indirection from the users of this interface.
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|
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In struct dma_buf_ops, unmap_dma_buf is defined as
|
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void (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *);
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void (*unmap_dma_buf)(struct dma_buf_attachment *,
|
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struct sg_table *,
|
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enum dma_data_direction);
|
||||
|
||||
unmap_dma_buf signifies the end-of-DMA for the attachment provided. Like
|
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map_dma_buf, this API also must be implemented by the exporter.
|
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|
|
|
|||
|
|
@ -18,7 +18,7 @@ memory image to a dump file on the local disk, or across the network to
|
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a remote system.
|
||||
|
||||
Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,
|
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and s390x architectures.
|
||||
s390x and arm architectures.
|
||||
|
||||
When the system kernel boots, it reserves a small section of memory for
|
||||
the dump-capture kernel. This ensures that ongoing Direct Memory Access
|
||||
|
|
@ -112,7 +112,7 @@ There are two possible methods of using Kdump.
|
|||
2) Or use the system kernel binary itself as dump-capture kernel and there is
|
||||
no need to build a separate dump-capture kernel. This is possible
|
||||
only with the architectures which support a relocatable kernel. As
|
||||
of today, i386, x86_64, ppc64 and ia64 architectures support relocatable
|
||||
of today, i386, x86_64, ppc64, ia64 and arm architectures support relocatable
|
||||
kernel.
|
||||
|
||||
Building a relocatable kernel is advantageous from the point of view that
|
||||
|
|
@ -241,6 +241,13 @@ Dump-capture kernel config options (Arch Dependent, ia64)
|
|||
kernel will be aligned to 64Mb, so if the start address is not then
|
||||
any space below the alignment point will be wasted.
|
||||
|
||||
Dump-capture kernel config options (Arch Dependent, arm)
|
||||
----------------------------------------------------------
|
||||
|
||||
- To use a relocatable kernel,
|
||||
Enable "AUTO_ZRELADDR" support under "Boot" options:
|
||||
|
||||
AUTO_ZRELADDR=y
|
||||
|
||||
Extended crashkernel syntax
|
||||
===========================
|
||||
|
|
@ -256,6 +263,10 @@ The syntax is:
|
|||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset]
|
||||
range=start-[end]
|
||||
|
||||
Please note, on arm, the offset is required.
|
||||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...]@offset
|
||||
range=start-[end]
|
||||
|
||||
'start' is inclusive and 'end' is exclusive.
|
||||
|
||||
For example:
|
||||
|
|
@ -296,6 +307,12 @@ Boot into System Kernel
|
|||
on the memory consumption of the kdump system. In general this is not
|
||||
dependent on the memory size of the production system.
|
||||
|
||||
On arm, use "crashkernel=Y@X". Note that the start address of the kernel
|
||||
will be aligned to 128MiB (0x08000000), so if the start address is not then
|
||||
any space below the alignment point may be overwritten by the dump-capture kernel,
|
||||
which means it is possible that the vmcore is not that precise as expected.
|
||||
|
||||
|
||||
Load the Dump-capture Kernel
|
||||
============================
|
||||
|
||||
|
|
@ -315,7 +332,8 @@ For ia64:
|
|||
- Use vmlinux or vmlinuz.gz
|
||||
For s390x:
|
||||
- Use image or bzImage
|
||||
|
||||
For arm:
|
||||
- Use zImage
|
||||
|
||||
If you are using a uncompressed vmlinux image then use following command
|
||||
to load dump-capture kernel.
|
||||
|
|
@ -331,6 +349,15 @@ to load dump-capture kernel.
|
|||
--initrd=<initrd-for-dump-capture-kernel> \
|
||||
--append="root=<root-dev> <arch-specific-options>"
|
||||
|
||||
If you are using a compressed zImage, then use following command
|
||||
to load dump-capture kernel.
|
||||
|
||||
kexec --type zImage -p <dump-capture-kernel-bzImage> \
|
||||
--initrd=<initrd-for-dump-capture-kernel> \
|
||||
--dtb=<dtb-for-dump-capture-kernel> \
|
||||
--append="root=<root-dev> <arch-specific-options>"
|
||||
|
||||
|
||||
Please note, that --args-linux does not need to be specified for ia64.
|
||||
It is planned to make this a no-op on that architecture, but for now
|
||||
it should be omitted
|
||||
|
|
@ -347,6 +374,9 @@ For ppc64:
|
|||
For s390x:
|
||||
"1 maxcpus=1 cgroup_disable=memory"
|
||||
|
||||
For arm:
|
||||
"1 maxcpus=1 reset_devices"
|
||||
|
||||
Notes on loading the dump-capture kernel:
|
||||
|
||||
* By default, the ELF headers are stored in ELF64 format to support
|
||||
|
|
|
|||
|
|
@ -2,26 +2,26 @@ this_cpu operations
|
|||
-------------------
|
||||
|
||||
this_cpu operations are a way of optimizing access to per cpu
|
||||
variables associated with the *currently* executing processor through
|
||||
the use of segment registers (or a dedicated register where the cpu
|
||||
permanently stored the beginning of the per cpu area for a specific
|
||||
processor).
|
||||
variables associated with the *currently* executing processor. This is
|
||||
done through the use of segment registers (or a dedicated register where
|
||||
the cpu permanently stored the beginning of the per cpu area for a
|
||||
specific processor).
|
||||
|
||||
The this_cpu operations add a per cpu variable offset to the processor
|
||||
specific percpu base and encode that operation in the instruction
|
||||
this_cpu operations add a per cpu variable offset to the processor
|
||||
specific per cpu base and encode that operation in the instruction
|
||||
operating on the per cpu variable.
|
||||
|
||||
This means there are no atomicity issues between the calculation of
|
||||
This means that there are no atomicity issues between the calculation of
|
||||
the offset and the operation on the data. Therefore it is not
|
||||
necessary to disable preempt or interrupts to ensure that the
|
||||
necessary to disable preemption or interrupts to ensure that the
|
||||
processor is not changed between the calculation of the address and
|
||||
the operation on the data.
|
||||
|
||||
Read-modify-write operations are of particular interest. Frequently
|
||||
processors have special lower latency instructions that can operate
|
||||
without the typical synchronization overhead but still provide some
|
||||
sort of relaxed atomicity guarantee. The x86 for example can execute
|
||||
RMV (Read Modify Write) instructions like inc/dec/cmpxchg without the
|
||||
without the typical synchronization overhead, but still provide some
|
||||
sort of relaxed atomicity guarantees. The x86, for example, can execute
|
||||
RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the
|
||||
lock prefix and the associated latency penalty.
|
||||
|
||||
Access to the variable without the lock prefix is not synchronized but
|
||||
|
|
@ -30,6 +30,38 @@ data specific to the currently executing processor. Only the current
|
|||
processor should be accessing that variable and therefore there are no
|
||||
concurrency issues with other processors in the system.
|
||||
|
||||
Please note that accesses by remote processors to a per cpu area are
|
||||
exceptional situations and may impact performance and/or correctness
|
||||
(remote write operations) of local RMW operations via this_cpu_*.
|
||||
|
||||
The main use of the this_cpu operations has been to optimize counter
|
||||
operations.
|
||||
|
||||
The following this_cpu() operations with implied preemption protection
|
||||
are defined. These operations can be used without worrying about
|
||||
preemption and interrupts.
|
||||
|
||||
this_cpu_add()
|
||||
this_cpu_read(pcp)
|
||||
this_cpu_write(pcp, val)
|
||||
this_cpu_add(pcp, val)
|
||||
this_cpu_and(pcp, val)
|
||||
this_cpu_or(pcp, val)
|
||||
this_cpu_add_return(pcp, val)
|
||||
this_cpu_xchg(pcp, nval)
|
||||
this_cpu_cmpxchg(pcp, oval, nval)
|
||||
this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
|
||||
this_cpu_sub(pcp, val)
|
||||
this_cpu_inc(pcp)
|
||||
this_cpu_dec(pcp)
|
||||
this_cpu_sub_return(pcp, val)
|
||||
this_cpu_inc_return(pcp)
|
||||
this_cpu_dec_return(pcp)
|
||||
|
||||
|
||||
Inner working of this_cpu operations
|
||||
------------------------------------
|
||||
|
||||
On x86 the fs: or the gs: segment registers contain the base of the
|
||||
per cpu area. It is then possible to simply use the segment override
|
||||
to relocate a per cpu relative address to the proper per cpu area for
|
||||
|
|
@ -48,22 +80,21 @@ results in a single instruction
|
|||
mov ax, gs:[x]
|
||||
|
||||
instead of a sequence of calculation of the address and then a fetch
|
||||
from that address which occurs with the percpu operations. Before
|
||||
from that address which occurs with the per cpu operations. Before
|
||||
this_cpu_ops such sequence also required preempt disable/enable to
|
||||
prevent the kernel from moving the thread to a different processor
|
||||
while the calculation is performed.
|
||||
|
||||
The main use of the this_cpu operations has been to optimize counter
|
||||
operations.
|
||||
Consider the following this_cpu operation:
|
||||
|
||||
this_cpu_inc(x)
|
||||
|
||||
results in the following single instruction (no lock prefix!)
|
||||
The above results in the following single instruction (no lock prefix!)
|
||||
|
||||
inc gs:[x]
|
||||
|
||||
instead of the following operations required if there is no segment
|
||||
register.
|
||||
register:
|
||||
|
||||
int *y;
|
||||
int cpu;
|
||||
|
|
@ -73,10 +104,10 @@ register.
|
|||
(*y)++;
|
||||
put_cpu();
|
||||
|
||||
Note that these operations can only be used on percpu data that is
|
||||
Note that these operations can only be used on per cpu data that is
|
||||
reserved for a specific processor. Without disabling preemption in the
|
||||
surrounding code this_cpu_inc() will only guarantee that one of the
|
||||
percpu counters is correctly incremented. However, there is no
|
||||
per cpu counters is correctly incremented. However, there is no
|
||||
guarantee that the OS will not move the process directly before or
|
||||
after the this_cpu instruction is executed. In general this means that
|
||||
the value of the individual counters for each processor are
|
||||
|
|
@ -86,9 +117,9 @@ that is of interest.
|
|||
Per cpu variables are used for performance reasons. Bouncing cache
|
||||
lines can be avoided if multiple processors concurrently go through
|
||||
the same code paths. Since each processor has its own per cpu
|
||||
variables no concurrent cacheline updates take place. The price that
|
||||
variables no concurrent cache line updates take place. The price that
|
||||
has to be paid for this optimization is the need to add up the per cpu
|
||||
counters when the value of the counter is needed.
|
||||
counters when the value of a counter is needed.
|
||||
|
||||
|
||||
Special operations:
|
||||
|
|
@ -100,33 +131,39 @@ Takes the offset of a per cpu variable (&x !) and returns the address
|
|||
of the per cpu variable that belongs to the currently executing
|
||||
processor. this_cpu_ptr avoids multiple steps that the common
|
||||
get_cpu/put_cpu sequence requires. No processor number is
|
||||
available. Instead the offset of the local per cpu area is simply
|
||||
added to the percpu offset.
|
||||
available. Instead, the offset of the local per cpu area is simply
|
||||
added to the per cpu offset.
|
||||
|
||||
Note that this operation is usually used in a code segment when
|
||||
preemption has been disabled. The pointer is then used to
|
||||
access local per cpu data in a critical section. When preemption
|
||||
is re-enabled this pointer is usually no longer useful since it may
|
||||
no longer point to per cpu data of the current processor.
|
||||
|
||||
|
||||
Per cpu variables and offsets
|
||||
-----------------------------
|
||||
|
||||
Per cpu variables have *offsets* to the beginning of the percpu
|
||||
Per cpu variables have *offsets* to the beginning of the per cpu
|
||||
area. They do not have addresses although they look like that in the
|
||||
code. Offsets cannot be directly dereferenced. The offset must be
|
||||
added to a base pointer of a percpu area of a processor in order to
|
||||
added to a base pointer of a per cpu area of a processor in order to
|
||||
form a valid address.
|
||||
|
||||
Therefore the use of x or &x outside of the context of per cpu
|
||||
operations is invalid and will generally be treated like a NULL
|
||||
pointer dereference.
|
||||
|
||||
In the context of per cpu operations
|
||||
DEFINE_PER_CPU(int, x);
|
||||
|
||||
x is a per cpu variable. Most this_cpu operations take a cpu
|
||||
variable.
|
||||
In the context of per cpu operations the above implies that x is a per
|
||||
cpu variable. Most this_cpu operations take a cpu variable.
|
||||
|
||||
&x is the *offset* a per cpu variable. this_cpu_ptr() takes
|
||||
the offset of a per cpu variable which makes this look a bit
|
||||
strange.
|
||||
int __percpu *p = &x;
|
||||
|
||||
&x and hence p is the *offset* of a per cpu variable. this_cpu_ptr()
|
||||
takes the offset of a per cpu variable which makes this look a bit
|
||||
strange.
|
||||
|
||||
|
||||
Operations on a field of a per cpu structure
|
||||
|
|
@ -152,7 +189,7 @@ If we have an offset to struct s:
|
|||
|
||||
struct s __percpu *ps = &p;
|
||||
|
||||
z = this_cpu_dec(ps->m);
|
||||
this_cpu_dec(ps->m);
|
||||
|
||||
z = this_cpu_inc_return(ps->n);
|
||||
|
||||
|
|
@ -172,29 +209,52 @@ if we do not make use of this_cpu ops later to manipulate fields:
|
|||
Variants of this_cpu ops
|
||||
-------------------------
|
||||
|
||||
this_cpu ops are interrupt safe. Some architecture do not support
|
||||
this_cpu ops are interrupt safe. Some architectures do not support
|
||||
these per cpu local operations. In that case the operation must be
|
||||
replaced by code that disables interrupts, then does the operations
|
||||
that are guaranteed to be atomic and then reenable interrupts. Doing
|
||||
that are guaranteed to be atomic and then re-enable interrupts. Doing
|
||||
so is expensive. If there are other reasons why the scheduler cannot
|
||||
change the processor we are executing on then there is no reason to
|
||||
disable interrupts. For that purpose the __this_cpu operations are
|
||||
provided. For example.
|
||||
disable interrupts. For that purpose the following __this_cpu operations
|
||||
are provided.
|
||||
|
||||
__this_cpu_inc(x);
|
||||
These operations have no guarantee against concurrent interrupts or
|
||||
preemption. If a per cpu variable is not used in an interrupt context
|
||||
and the scheduler cannot preempt, then they are safe. If any interrupts
|
||||
still occur while an operation is in progress and if the interrupt too
|
||||
modifies the variable, then RMW actions can not be guaranteed to be
|
||||
safe.
|
||||
|
||||
Will increment x and will not fallback to code that disables
|
||||
__this_cpu_add()
|
||||
__this_cpu_read(pcp)
|
||||
__this_cpu_write(pcp, val)
|
||||
__this_cpu_add(pcp, val)
|
||||
__this_cpu_and(pcp, val)
|
||||
__this_cpu_or(pcp, val)
|
||||
__this_cpu_add_return(pcp, val)
|
||||
__this_cpu_xchg(pcp, nval)
|
||||
__this_cpu_cmpxchg(pcp, oval, nval)
|
||||
__this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
|
||||
__this_cpu_sub(pcp, val)
|
||||
__this_cpu_inc(pcp)
|
||||
__this_cpu_dec(pcp)
|
||||
__this_cpu_sub_return(pcp, val)
|
||||
__this_cpu_inc_return(pcp)
|
||||
__this_cpu_dec_return(pcp)
|
||||
|
||||
|
||||
Will increment x and will not fall-back to code that disables
|
||||
interrupts on platforms that cannot accomplish atomicity through
|
||||
address relocation and a Read-Modify-Write operation in the same
|
||||
instruction.
|
||||
|
||||
|
||||
|
||||
&this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n)
|
||||
--------------------------------------------
|
||||
|
||||
The first operation takes the offset and forms an address and then
|
||||
adds the offset of the n field.
|
||||
adds the offset of the n field. This may result in two add
|
||||
instructions emitted by the compiler.
|
||||
|
||||
The second one first adds the two offsets and then does the
|
||||
relocation. IMHO the second form looks cleaner and has an easier time
|
||||
|
|
@ -202,4 +262,73 @@ with (). The second form also is consistent with the way
|
|||
this_cpu_read() and friends are used.
|
||||
|
||||
|
||||
Christoph Lameter, April 3rd, 2013
|
||||
Remote access to per cpu data
|
||||
------------------------------
|
||||
|
||||
Per cpu data structures are designed to be used by one cpu exclusively.
|
||||
If you use the variables as intended, this_cpu_ops() are guaranteed to
|
||||
be "atomic" as no other CPU has access to these data structures.
|
||||
|
||||
There are special cases where you might need to access per cpu data
|
||||
structures remotely. It is usually safe to do a remote read access
|
||||
and that is frequently done to summarize counters. Remote write access
|
||||
something which could be problematic because this_cpu ops do not
|
||||
have lock semantics. A remote write may interfere with a this_cpu
|
||||
RMW operation.
|
||||
|
||||
Remote write accesses to percpu data structures are highly discouraged
|
||||
unless absolutely necessary. Please consider using an IPI to wake up
|
||||
the remote CPU and perform the update to its per cpu area.
|
||||
|
||||
To access per-cpu data structure remotely, typically the per_cpu_ptr()
|
||||
function is used:
|
||||
|
||||
|
||||
DEFINE_PER_CPU(struct data, datap);
|
||||
|
||||
struct data *p = per_cpu_ptr(&datap, cpu);
|
||||
|
||||
This makes it explicit that we are getting ready to access a percpu
|
||||
area remotely.
|
||||
|
||||
You can also do the following to convert the datap offset to an address
|
||||
|
||||
struct data *p = this_cpu_ptr(&datap);
|
||||
|
||||
but, passing of pointers calculated via this_cpu_ptr to other cpus is
|
||||
unusual and should be avoided.
|
||||
|
||||
Remote access are typically only for reading the status of another cpus
|
||||
per cpu data. Write accesses can cause unique problems due to the
|
||||
relaxed synchronization requirements for this_cpu operations.
|
||||
|
||||
One example that illustrates some concerns with write operations is
|
||||
the following scenario that occurs because two per cpu variables
|
||||
share a cache-line but the relaxed synchronization is applied to
|
||||
only one process updating the cache-line.
|
||||
|
||||
Consider the following example
|
||||
|
||||
|
||||
struct test {
|
||||
atomic_t a;
|
||||
int b;
|
||||
};
|
||||
|
||||
DEFINE_PER_CPU(struct test, onecacheline);
|
||||
|
||||
There is some concern about what would happen if the field 'a' is updated
|
||||
remotely from one processor and the local processor would use this_cpu ops
|
||||
to update field b. Care should be taken that such simultaneous accesses to
|
||||
data within the same cache line are avoided. Also costly synchronization
|
||||
may be necessary. IPIs are generally recommended in such scenarios instead
|
||||
of a remote write to the per cpu area of another processor.
|
||||
|
||||
Even in cases where the remote writes are rare, please bear in
|
||||
mind that a remote write will evict the cache line from the processor
|
||||
that most likely will access it. If the processor wakes up and finds a
|
||||
missing local cache line of a per cpu area, its performance and hence
|
||||
the wake up times will be affected.
|
||||
|
||||
Christoph Lameter, August 4th, 2014
|
||||
Pranith Kumar, Aug 2nd, 2014
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ invlpg instruction (or instructions _near_ it) show up high in
|
|||
profiles. If you believe that individual invalidations being
|
||||
called too often, you can lower the tunable:
|
||||
|
||||
/sys/debug/kernel/x86/tlb_single_page_flush_ceiling
|
||||
/sys/kernel/debug/x86/tlb_single_page_flush_ceiling
|
||||
|
||||
This will cause us to do the global flush for more cases.
|
||||
Lowering it to 0 will disable the use of the individual flushes.
|
||||
|
|
|
|||
57
MAINTAINERS
57
MAINTAINERS
|
|
@ -1288,9 +1288,15 @@ F: drivers/scsi/arm/
|
|||
ARM/Rockchip SoC support
|
||||
M: Heiko Stuebner <heiko@sntech.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-rockchip@lists.infradead.org
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/rk3*
|
||||
F: arch/arm/mach-rockchip/
|
||||
F: drivers/clk/rockchip/
|
||||
F: drivers/i2c/busses/i2c-rk3x.c
|
||||
F: drivers/*/*rockchip*
|
||||
F: drivers/*/*/*rockchip*
|
||||
F: sound/soc/rockchip/
|
||||
|
||||
ARM/SAMSUNG ARM ARCHITECTURES
|
||||
M: Ben Dooks <ben-linux@fluff.org>
|
||||
|
|
@ -1854,6 +1860,12 @@ S: Orphan
|
|||
F: Documentation/filesystems/befs.txt
|
||||
F: fs/befs/
|
||||
|
||||
BECKHOFF CX5020 ETHERCAT MASTER DRIVER
|
||||
M: Dariusz Marcinkiewicz <reksio@newterm.pl>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/ec_bhf.c
|
||||
|
||||
BFS FILE SYSTEM
|
||||
M: "Tigran A. Aivazian" <tigran@aivazian.fsnet.co.uk>
|
||||
S: Maintained
|
||||
|
|
@ -2070,7 +2082,7 @@ S: Supported
|
|||
F: drivers/scsi/bnx2i/
|
||||
|
||||
BROADCOM KONA GPIO DRIVER
|
||||
M: Markus Mayer <markus.mayer@linaro.org>
|
||||
M: Ray Jui <rjui@broadcom.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
S: Supported
|
||||
F: drivers/gpio/gpio-bcm-kona.c
|
||||
|
|
@ -3126,6 +3138,17 @@ F: include/linux/host1x.h
|
|||
F: include/uapi/drm/tegra_drm.h
|
||||
F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
|
||||
|
||||
DRM DRIVERS FOR RENESAS
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-sh@vger.kernel.org
|
||||
T: git git://people.freedesktop.org/~airlied/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/rcar-du/
|
||||
F: drivers/gpu/drm/shmobile/
|
||||
F: include/linux/platform_data/rcar-du.h
|
||||
F: include/linux/platform_data/shmob_drm.h
|
||||
|
||||
DSBR100 USB FM RADIO DRIVER
|
||||
M: Alexey Klimov <klimov.linux@gmail.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
|
|
@ -3854,10 +3877,13 @@ F: drivers/tty/serial/ucc_uart.c
|
|||
|
||||
FREESCALE SOC SOUND DRIVERS
|
||||
M: Timur Tabi <timur@tabi.org>
|
||||
M: Nicolin Chen <nicoleotsuka@gmail.com>
|
||||
M: Xiubo Li <Li.Xiubo@freescale.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Maintained
|
||||
F: sound/soc/fsl/fsl*
|
||||
F: sound/soc/fsl/imx*
|
||||
F: sound/soc/fsl/mpc8610_hpcd.c
|
||||
|
||||
FREEVXFS FILESYSTEM
|
||||
|
|
@ -4457,6 +4483,13 @@ F: include/linux/i2c-*.h
|
|||
F: include/uapi/linux/i2c.h
|
||||
F: include/uapi/linux/i2c-*.h
|
||||
|
||||
I2C ACPI SUPPORT
|
||||
M: Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
L: linux-acpi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/i2c-acpi.c
|
||||
|
||||
I2C-TAOS-EVM DRIVER
|
||||
M: Jean Delvare <jdelvare@suse.de>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
|
|
@ -5986,6 +6019,12 @@ T: git git://linuxtv.org/media_tree.git
|
|||
S: Maintained
|
||||
F: drivers/media/radio/radio-mr800.c
|
||||
|
||||
MRF24J40 IEEE 802.15.4 RADIO DRIVER
|
||||
M: Alan Ott <alan@signal11.us>
|
||||
L: linux-wpan@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ieee802154/mrf24j40.c
|
||||
|
||||
MSI LAPTOP SUPPORT
|
||||
M: "Lee, Chun-Yi" <jlee@suse.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
|
|
@ -6872,6 +6911,14 @@ S: Supported
|
|||
F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
|
||||
F: drivers/pci/host/pci-tegra.c
|
||||
|
||||
PCI DRIVER FOR TI DRA7XX
|
||||
M: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/pci/ti-pci.txt
|
||||
F: drivers/pci/host/pci-dra7xx.c
|
||||
|
||||
PCI DRIVER FOR RENESAS R-CAR
|
||||
M: Simon Horman <horms@verge.net.au>
|
||||
L: linux-pci@vger.kernel.org
|
||||
|
|
@ -9537,6 +9584,14 @@ S: Maintained
|
|||
F: Documentation/usb/ohci.txt
|
||||
F: drivers/usb/host/ohci*
|
||||
|
||||
USB OVER IP DRIVER
|
||||
M: Valentina Manea <valentina.manea.m@gmail.com>
|
||||
M: Shuah Khan <shuah.kh@samsung.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/usb/usbip/
|
||||
F: tools/usb/usbip/
|
||||
|
||||
USB PEGASUS DRIVER
|
||||
M: Petko Manolov <petkan@nucleusys.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 17
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Shuffling Zombie Juror
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -500,10 +500,14 @@ extern inline void writeq(u64 b, volatile void __iomem *addr)
|
|||
#define outb_p outb
|
||||
#define outw_p outw
|
||||
#define outl_p outl
|
||||
#define readb_relaxed(addr) __raw_readb(addr)
|
||||
#define readw_relaxed(addr) __raw_readw(addr)
|
||||
#define readl_relaxed(addr) __raw_readl(addr)
|
||||
#define readq_relaxed(addr) __raw_readq(addr)
|
||||
#define readb_relaxed(addr) __raw_readb(addr)
|
||||
#define readw_relaxed(addr) __raw_readw(addr)
|
||||
#define readl_relaxed(addr) __raw_readl(addr)
|
||||
#define readq_relaxed(addr) __raw_readq(addr)
|
||||
#define writeb_relaxed(b, addr) __raw_writeb(b, addr)
|
||||
#define writew_relaxed(b, addr) __raw_writew(b, addr)
|
||||
#define writel_relaxed(b, addr) __raw_writel(b, addr)
|
||||
#define writeq_relaxed(b, addr) __raw_writeq(b, addr)
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#include <uapi/asm/unistd.h>
|
||||
|
||||
#define NR_SYSCALLS 508
|
||||
#define NR_SYSCALLS 511
|
||||
|
||||
#define __ARCH_WANT_OLD_READDIR
|
||||
#define __ARCH_WANT_STAT64
|
||||
|
|
|
|||
|
|
@ -469,5 +469,8 @@
|
|||
#define __NR_process_vm_writev 505
|
||||
#define __NR_kcmp 506
|
||||
#define __NR_finit_module 507
|
||||
#define __NR_sched_setattr 508
|
||||
#define __NR_sched_getattr 509
|
||||
#define __NR_renameat2 510
|
||||
|
||||
#endif /* _UAPI_ALPHA_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -526,6 +526,9 @@ sys_call_table:
|
|||
.quad sys_process_vm_writev /* 505 */
|
||||
.quad sys_kcmp
|
||||
.quad sys_finit_module
|
||||
.quad sys_sched_setattr
|
||||
.quad sys_sched_getattr
|
||||
.quad sys_renameat2 /* 510 */
|
||||
|
||||
.size sys_call_table, . - sys_call_table
|
||||
.type sys_call_table, @object
|
||||
|
|
|
|||
|
|
@ -581,6 +581,7 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
|
|||
tot_sz -= sz;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
/*
|
||||
* General purpose helper to make I and D cache lines consistent.
|
||||
|
|
|
|||
|
|
@ -1983,8 +1983,6 @@ config XIP_PHYS_ADDR
|
|||
config KEXEC
|
||||
bool "Kexec system call (EXPERIMENTAL)"
|
||||
depends on (!SMP || PM_SLEEP_SMP)
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ gpio1: gpio@4ae10000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@48055000 {
|
||||
|
|
@ -256,7 +256,7 @@ gpio2: gpio@48055000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@48057000 {
|
||||
|
|
@ -267,7 +267,7 @@ gpio3: gpio@48057000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@48059000 {
|
||||
|
|
@ -278,7 +278,7 @@ gpio4: gpio@48059000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@4805b000 {
|
||||
|
|
@ -289,7 +289,7 @@ gpio5: gpio@4805b000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@4805d000 {
|
||||
|
|
@ -300,7 +300,7 @@ gpio6: gpio@4805d000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@48051000 {
|
||||
|
|
@ -311,7 +311,7 @@ gpio7: gpio@48051000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio8: gpio@48053000 {
|
||||
|
|
@ -322,7 +322,7 @@ gpio8: gpio@48053000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
|
|
|
|||
|
|
@ -134,6 +134,8 @@ xusbxti {
|
|||
i2c@13860000 {
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <400000>;
|
||||
status = "okay";
|
||||
|
||||
usb3503: usb3503@08 {
|
||||
|
|
@ -148,6 +150,10 @@ usb3503: usb3503@08 {
|
|||
|
||||
max77686: pmic@09 {
|
||||
compatible = "maxim,max77686";
|
||||
interrupt-parent = <&gpx3>;
|
||||
interrupts = <2 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max77686_irq>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
|
|
@ -368,4 +374,11 @@ gpio_power_key: power_key {
|
|||
samsung,pins = "gpx1-3";
|
||||
samsung,pin-pud = <0>;
|
||||
};
|
||||
|
||||
max77686_irq: max77686-irq {
|
||||
samsung,pins = "gpx3-2";
|
||||
samsung,pin-function = <0>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@ MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
|
|||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -38,6 +44,8 @@ &i2c1 {
|
|||
|
||||
pmic: mc34708@8 {
|
||||
compatible = "fsl,mc34708";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
reg = <0x08>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <23 0x8>;
|
||||
|
|
|
|||
|
|
@ -731,7 +731,7 @@ vpu: vpu@63ff4000 {
|
|||
compatible = "fsl,imx53-vpu";
|
||||
reg = <0x63ff4000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks IMX5_CLK_VPU_GATE>,
|
||||
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
||||
<&clks IMX5_CLK_VPU_GATE>;
|
||||
clock-names = "per", "ahb";
|
||||
resets = <&src 1>;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ reg_usbotg_vbus: usb-otg-vbus {
|
|||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
model = "On-board SPDIF";
|
||||
/* IMX6 doesn't implement this yet */
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-out;
|
||||
|
|
@ -181,11 +181,13 @@ &spdif {
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
disable-over-current;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
disable-over-current;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ &fec {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 23 0>;
|
||||
phy-reset-gpios = <&gpio1 25 0>;
|
||||
phy-supply = <&vgen2_1v2_eth>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -339,6 +339,7 @@ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
|||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ reg_usbotg_vbus: usb-otg-vbus {
|
|||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
model = "Integrated SPDIF";
|
||||
/* IMX6 doesn't implement this yet */
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-out;
|
||||
|
|
@ -130,16 +130,23 @@ pinctrl_cubox_i_spdif: cubox-i-spdif {
|
|||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
|
||||
pinctrl_cubox_i_usbotg: cubox-i-usbotg {
|
||||
/*
|
||||
* The Cubox-i pulls this low, but as it's pointless
|
||||
* The Cubox-i pulls ID low, but as it's pointless
|
||||
* leaving it as a pull-up, even if it is just 10uA.
|
||||
*/
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
||||
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
|
||||
|
|
@ -173,13 +180,15 @@ &spdif {
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ &iomuxc {
|
|||
enet {
|
||||
pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
/* AR8035 reset */
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@
|
|||
#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
|
||||
|
|
@ -96,7 +96,7 @@
|
|||
#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
|
||||
|
|
@ -213,7 +213,7 @@
|
|||
#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
|
||||
#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
|
||||
#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1
|
||||
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
|
||||
|
|
@ -254,7 +254,7 @@
|
|||
#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
|
||||
#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
|
||||
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3
|
||||
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
|
||||
|
|
@ -352,7 +352,7 @@
|
|||
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
|
||||
|
|
@ -404,7 +404,7 @@
|
|||
#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3
|
||||
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
|
||||
|
|
@ -423,7 +423,7 @@
|
|||
#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3
|
||||
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
|
||||
|
|
@ -815,7 +815,7 @@
|
|||
#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1
|
||||
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
|
||||
|
|
@ -957,7 +957,7 @@
|
|||
#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
|
||||
#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
|
||||
|
|
@ -1236,7 +1236,7 @@
|
|||
#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
|
||||
#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2
|
||||
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
|
||||
|
|
@ -1315,7 +1315,7 @@
|
|||
#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
|
||||
#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
|
||||
|
|
@ -1409,7 +1409,7 @@
|
|||
#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3
|
||||
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
|
||||
|
|
@ -1510,7 +1510,7 @@
|
|||
#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1
|
||||
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
|
||||
|
|
|
|||
|
|
@ -292,6 +292,7 @@ &twl_gpio {
|
|||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ twl_audio: audio {
|
|||
};
|
||||
|
||||
twl_power: power {
|
||||
compatible = "ti,twl4030-power-n900";
|
||||
compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ nand@1,0 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 0x08000000>;
|
||||
ti,nand-ecc-opt = "ham1";
|
||||
ti,nand-ecc-opt = "sw";
|
||||
nand-bus-width = <8>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <36>;
|
||||
|
|
|
|||
|
|
@ -367,10 +367,12 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
|
|||
|
||||
l3_iclk_div: l3_iclk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
compatible = "ti,divider-clock";
|
||||
ti,max-div = <2>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x100>;
|
||||
clocks = <&dpll_core_h12x2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
gpu_l3_iclk: gpu_l3_iclk {
|
||||
|
|
@ -383,10 +385,12 @@ gpu_l3_iclk: gpu_l3_iclk {
|
|||
|
||||
l4_root_clk_div: l4_root_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
compatible = "ti,divider-clock";
|
||||
ti,max-div = <2>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x100>;
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
slimbus1_slimbus_clk: slimbus1_slimbus_clk {
|
||||
|
|
|
|||
|
|
@ -275,11 +275,6 @@ msiof0_pins: spi1 {
|
|||
renesas,function = "msiof0";
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6 {
|
||||
renesas,groups = "i2c6";
|
||||
renesas,function = "i2c6";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
|
|
@ -420,8 +415,6 @@ eeprom@50 {
|
|||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -149,6 +149,8 @@ vcc28_cif: regulator@12 {
|
|||
&mmc0 { /* sdmmc */
|
||||
num-slots = <1>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
|
||||
slot@0 {
|
||||
|
|
|
|||
|
|
@ -179,6 +179,8 @@ vcc28: REG12 {
|
|||
&mmc0 {
|
||||
num-slots = <1>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
|
||||
slot@0 {
|
||||
|
|
|
|||
|
|
@ -660,6 +660,8 @@ i2c0: i2c@01c2ac00 {
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@01c2b000 {
|
||||
|
|
@ -670,6 +672,8 @@ i2c1: i2c@01c2b000 {
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@01c2b400 {
|
||||
|
|
@ -680,6 +684,8 @@ i2c2: i2c@01c2b400 {
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@01c2b800 {
|
||||
|
|
@ -690,6 +696,8 @@ i2c3: i2c@01c2b800 {
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 3>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gmac: ethernet@01c30000 {
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@ pmic: tps65911@2d {
|
|||
vcc4-supply = <&sys_3v3_reg>;
|
||||
vcc5-supply = <&sys_3v3_reg>;
|
||||
vcc6-supply = <&vio_reg>;
|
||||
vcc7-supply = <&sys_5v0_reg>;
|
||||
vcc7-supply = <&charge_pump_5v0_reg>;
|
||||
vccio-supply = <&sys_3v3_reg>;
|
||||
|
||||
regulators {
|
||||
|
|
@ -674,5 +674,14 @@ sys_3v3_reg: regulator@100 {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
charge_pump_5v0_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -201,7 +201,7 @@ pmic: tps65911@2d {
|
|||
vcc4-supply = <&sys_3v3_reg>;
|
||||
vcc5-supply = <&sys_3v3_reg>;
|
||||
vcc6-supply = <&vio_reg>;
|
||||
vcc7-supply = <&sys_5v0_reg>;
|
||||
vcc7-supply = <&charge_pump_5v0_reg>;
|
||||
vccio-supply = <&sys_3v3_reg>;
|
||||
|
||||
regulators {
|
||||
|
|
@ -373,5 +373,14 @@ sys_3v3_reg: regulator@100 {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
charge_pump_5v0_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -83,10 +83,6 @@ v2v1: regulator-v2v1 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
clk32kg: regulator-clk32kg {
|
||||
compatible = "ti,twl6030-clk32kg";
|
||||
};
|
||||
|
||||
twl_usb_comparator: usb-comparator {
|
||||
compatible = "ti,twl6030-usb";
|
||||
interrupts = <4>, <10>;
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ VF610_PAD_PTB22__DSPI0_SCK 0x1182
|
|||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,fsl,pins = <
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
|
||||
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
|
||||
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
|
||||
|
|
|
|||
|
|
@ -472,7 +472,6 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
|
|||
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
|
||||
"isb \n\t" \
|
||||
"bl v7_flush_dcache_"__stringify(level)" \n\t" \
|
||||
"clrex \n\t" \
|
||||
"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
|
||||
"bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
|
||||
"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
|
||||
#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
|
||||
#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
|
||||
#define ARM_CPU_PART_MASK 0xff00fff0
|
||||
|
||||
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
|
||||
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
|
||||
|
|
@ -179,7 +180,7 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
|
|||
*/
|
||||
static inline unsigned int __attribute_const__ read_cpuid_part(void)
|
||||
{
|
||||
return read_cpuid_id() & 0xff00fff0;
|
||||
return read_cpuid_id() & ARM_CPU_PART_MASK;
|
||||
}
|
||||
|
||||
static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t;
|
|||
#define R_ARM_ABS32 2
|
||||
#define R_ARM_CALL 28
|
||||
#define R_ARM_JUMP24 29
|
||||
#define R_ARM_TARGET1 38
|
||||
#define R_ARM_V4BX 40
|
||||
#define R_ARM_PREL31 42
|
||||
#define R_ARM_MOVW_ABS_NC 43
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <linux/cpumask.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
/*
|
||||
|
|
@ -25,6 +26,20 @@ static inline bool is_smp(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* smp_cpuid_part() - return part id for a given cpu
|
||||
* @cpu: logical cpu id.
|
||||
*
|
||||
* Return: part id of logical cpu passed as argument.
|
||||
*/
|
||||
static inline unsigned int smp_cpuid_part(int cpu)
|
||||
{
|
||||
struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpu);
|
||||
|
||||
return is_smp() ? cpu_info->cpuid & ARM_CPU_PART_MASK :
|
||||
read_cpuid_part();
|
||||
}
|
||||
|
||||
/* all SMP configurations have the extended CPUID registers */
|
||||
#ifndef CONFIG_MMU
|
||||
#define tlb_ops_need_broadcast() 0
|
||||
|
|
|
|||
|
|
@ -208,26 +208,21 @@
|
|||
#endif
|
||||
.endif
|
||||
msr spsr_cxsf, \rpsr
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
ldr r0, [sp]
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex @ clear the exclusive monitor
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
#else
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
sub r0, sp, #4 @ uninhabited address
|
||||
strex r1, r2, [r0] @ clear the exclusive monitor
|
||||
#endif
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
.endm
|
||||
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC]! @ get pc
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex @ clear the exclusive monitor
|
||||
#endif
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
|
||||
|
|
@ -261,7 +256,10 @@
|
|||
.endif
|
||||
ldr lr, [sp, #S_SP] @ top of the stack
|
||||
ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
|
||||
clrex @ clear the exclusive monitor
|
||||
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor
|
||||
|
||||
stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
|
||||
ldmia sp, {r0 - r12}
|
||||
mov sp, lr
|
||||
|
|
@ -282,13 +280,16 @@
|
|||
.endm
|
||||
#else /* ifdef CONFIG_CPU_V7M */
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
clrex @ clear the exclusive monitor
|
||||
mov r2, sp
|
||||
load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC] @ get pc
|
||||
add sp, sp, #\offset + S_SP
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - r12} @ get calling r1 - r12
|
||||
.else
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
|
|||
break;
|
||||
|
||||
case R_ARM_ABS32:
|
||||
case R_ARM_TARGET1:
|
||||
*(u32 *)loc += sym->st_value;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -36,5 +36,4 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
|
|||
|
||||
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
|
||||
obj-y += brcmstb.o
|
||||
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BRCMSTB_H__
|
||||
#define __BRCMSTB_H__
|
||||
|
||||
void brcmstb_secondary_startup(void);
|
||||
|
||||
#endif /* __BRCMSTB_H__ */
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* SMP boot code for secondary CPUs
|
||||
* Based on arch/arm/mach-tegra/headsmp.S
|
||||
*
|
||||
* Copyright (C) 2010 NVIDIA, Inc.
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/assembler.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
.section ".text.head", "ax"
|
||||
|
||||
ENTRY(brcmstb_secondary_startup)
|
||||
/*
|
||||
* Ensure CPU is in a sane state by disabling all IRQs and switching
|
||||
* into SVC mode.
|
||||
*/
|
||||
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
|
||||
|
||||
bl v7_invalidate_l1
|
||||
b secondary_startup
|
||||
ENDPROC(brcmstb_secondary_startup)
|
||||
|
|
@ -1,363 +0,0 @@
|
|||
/*
|
||||
* Broadcom STB CPU SMP and hotplug support for ARM
|
||||
*
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "brcmstb.h"
|
||||
|
||||
enum {
|
||||
ZONE_MAN_CLKEN_MASK = BIT(0),
|
||||
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
|
||||
ZONE_MAN_MEM_PWR_MASK = BIT(4),
|
||||
ZONE_RESERVED_1_MASK = BIT(5),
|
||||
ZONE_MAN_ISO_CNTL_MASK = BIT(6),
|
||||
ZONE_MANUAL_CONTROL_MASK = BIT(7),
|
||||
ZONE_PWR_DN_REQ_MASK = BIT(9),
|
||||
ZONE_PWR_UP_REQ_MASK = BIT(10),
|
||||
ZONE_BLK_RST_ASSERT_MASK = BIT(12),
|
||||
ZONE_PWR_OFF_STATE_MASK = BIT(25),
|
||||
ZONE_PWR_ON_STATE_MASK = BIT(26),
|
||||
ZONE_DPG_PWR_STATE_MASK = BIT(28),
|
||||
ZONE_MEM_PWR_STATE_MASK = BIT(29),
|
||||
ZONE_RESET_STATE_MASK = BIT(31),
|
||||
CPU0_PWR_ZONE_CTRL_REG = 1,
|
||||
CPU_RESET_CONFIG_REG = 2,
|
||||
};
|
||||
|
||||
static void __iomem *cpubiuctrl_block;
|
||||
static void __iomem *hif_cont_block;
|
||||
static u32 cpu0_pwr_zone_ctrl_reg;
|
||||
static u32 cpu_rst_cfg_reg;
|
||||
static u32 hif_cont_reg;
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
|
||||
|
||||
static int per_cpu_sw_state_rd(u32 cpu)
|
||||
{
|
||||
sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
return per_cpu(per_cpu_sw_state, cpu);
|
||||
}
|
||||
|
||||
static void per_cpu_sw_state_wr(u32 cpu, int val)
|
||||
{
|
||||
per_cpu(per_cpu_sw_state, cpu) = val;
|
||||
dmb();
|
||||
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
dsb_sev();
|
||||
}
|
||||
#else
|
||||
static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
|
||||
#endif
|
||||
|
||||
static void __iomem *pwr_ctrl_get_base(u32 cpu)
|
||||
{
|
||||
void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
|
||||
base += (cpu_logical_map(cpu) * 4);
|
||||
return base;
|
||||
}
|
||||
|
||||
static u32 pwr_ctrl_rd(u32 cpu)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
return readl_relaxed(base);
|
||||
}
|
||||
|
||||
static void pwr_ctrl_wr(u32 cpu, u32 val)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
writel(val, base);
|
||||
}
|
||||
|
||||
static void cpu_rst_cfg_set(u32 cpu, int set)
|
||||
{
|
||||
u32 val;
|
||||
val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
if (set)
|
||||
val |= BIT(cpu_logical_map(cpu));
|
||||
else
|
||||
val &= ~BIT(cpu_logical_map(cpu));
|
||||
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
}
|
||||
|
||||
static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
|
||||
{
|
||||
const int reg_ofs = cpu_logical_map(cpu) * 8;
|
||||
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
|
||||
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_boot(u32 cpu)
|
||||
{
|
||||
pr_info("SMP: Booting CPU%d...\n", cpu);
|
||||
|
||||
/*
|
||||
* set the reset vector to point to the secondary_startup
|
||||
* routine
|
||||
*/
|
||||
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
|
||||
|
||||
/* unhalt the cpu */
|
||||
cpu_rst_cfg_set(cpu, 0);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_power_on(u32 cpu)
|
||||
{
|
||||
/*
|
||||
* The secondary cores power was cut, so we must go through
|
||||
* power-on initialization.
|
||||
*/
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering up CPU%d...\n", cpu);
|
||||
|
||||
/* Request zone power up */
|
||||
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
|
||||
|
||||
/* Wait for the power up FSM to complete */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 1);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_get_power_state(u32 cpu)
|
||||
{
|
||||
int tmp = pwr_ctrl_rd(cpu);
|
||||
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
||||
static void brcmstb_cpu_die(u32 cpu)
|
||||
{
|
||||
v7_exit_coherency_flush(all);
|
||||
|
||||
/* Prevent all interrupts from reaching this CPU. */
|
||||
arch_local_irq_disable();
|
||||
|
||||
/*
|
||||
* Final full barrier to ensure everything before this instruction has
|
||||
* quiesced.
|
||||
*/
|
||||
isb();
|
||||
dsb();
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 0);
|
||||
|
||||
/* Sit and wait to die */
|
||||
wfi();
|
||||
|
||||
/* We should never get here... */
|
||||
panic("Spurious interrupt on CPU %d received!\n", cpu);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_kill(u32 cpu)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering down CPU%d...\n", cpu);
|
||||
|
||||
while (per_cpu_sw_state_rd(cpu))
|
||||
;
|
||||
|
||||
/* Program zone reset */
|
||||
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
|
||||
ZONE_PWR_DN_REQ_MASK);
|
||||
|
||||
/* Verify zone reset */
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
if (!(tmp & ZONE_RESET_STATE_MASK))
|
||||
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
|
||||
__func__, cpu);
|
||||
|
||||
/* Wait for power down */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
|
||||
|
||||
/* Settle-time from Broadcom-internal DVT reference code */
|
||||
udelay(7);
|
||||
|
||||
/* Assert reset on the CPU */
|
||||
cpu_rst_cfg_set(cpu, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cpu";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cpubiuctrl_block = of_iomap(syscon_np, 0);
|
||||
if (!cpubiuctrl_block) {
|
||||
pr_err("iomap failed for cpubiuctrl_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
|
||||
&cpu0_pwr_zone_ctrl_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 1st entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
|
||||
&cpu_rst_cfg_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init setup_hifcont_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cont";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
hif_cont_block = of_iomap(syscon_np, 0);
|
||||
if (!hif_cont_block) {
|
||||
pr_err("iomap failed for hif_cont_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* offset is at top of hif_cont_block */
|
||||
hif_cont_reg = 0;
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
|
||||
{
|
||||
int rc;
|
||||
struct device_node *np;
|
||||
char *name;
|
||||
|
||||
name = "brcm,brcmstb-smpboot";
|
||||
np = of_find_compatible_node(NULL, NULL, name);
|
||||
if (!np) {
|
||||
pr_err("can't find compatible node %s\n", name);
|
||||
return;
|
||||
}
|
||||
|
||||
rc = setup_hifcpubiuctrl_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
rc = setup_hifcont_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static void brcmstb_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/* Bring up power to the core if necessary */
|
||||
if (brcmstb_cpu_get_power_state(cpu) == 0)
|
||||
brcmstb_cpu_power_on(cpu);
|
||||
|
||||
brcmstb_cpu_boot(cpu);
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct smp_operations brcmstb_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
|
||||
.smp_secondary_init = brcmstb_secondary_init,
|
||||
.smp_boot_secondary = brcmstb_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = brcmstb_cpu_kill,
|
||||
.cpu_die = brcmstb_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
|
||||
|
|
@ -43,7 +43,6 @@
|
|||
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
|
||||
"isb\n\t"\
|
||||
"bl v7_flush_dcache_"__stringify(level)"\n\t" \
|
||||
"clrex\n\t"\
|
||||
"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
|
||||
"bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
|
||||
/* Dummy Load of a device register to avoid Erratum 799270 */ \
|
||||
|
|
|
|||
|
|
@ -85,7 +85,6 @@ config SOC_IMX25
|
|||
|
||||
config SOC_IMX27
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select CPU_ARM926T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
|
@ -659,7 +658,6 @@ comment "Device tree only"
|
|||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select HAVE_IMX_SRC
|
||||
select MXC_TZIC
|
||||
|
||||
|
|
|
|||
|
|
@ -93,9 +93,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
|
|||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
|
||||
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
|
||||
ifdef CONFIG_SOC_IMX6
|
||||
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
endif
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
|
||||
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
|
||||
|
|
|
|||
|
|
@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
if (cpu_is_imx6dl()) {
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
|
||||
}
|
||||
|
||||
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
|
|
@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
if (cpu_is_imx6q()) {
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
}
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
|
|
|
|||
|
|
@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
|
|||
ldr r6, [r11, #0x0]
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
ldr r6, [r11, #0x0]
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
|
||||
ldr r6, [r11, #0x0]
|
||||
|
||||
/* use r11 to store the IO address */
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
|
|||
board_nand_data.nr_parts = nr_parts;
|
||||
board_nand_data.devsize = nand_type;
|
||||
|
||||
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
|
||||
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
|
||||
gpmc_nand_init(&board_nand_data, gpmc_t);
|
||||
}
|
||||
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
|
||||
|
|
|
|||
|
|
@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
|
|||
return 0;
|
||||
|
||||
/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
|
||||
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
|
||||
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
|
||||
ecc_opt == OMAP_ECC_HAM1_CODE_SW)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1403,8 +1403,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
|
|||
pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
|
||||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
|
||||
|
||||
if (!strcmp(s, "sw"))
|
||||
gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
|
||||
else if (!strcmp(s, "ham1") ||
|
||||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
|
||||
gpmc_nand_data->ecc_opt =
|
||||
OMAP_ECC_HAM1_CODE_HW;
|
||||
else if (!strcmp(s, "bch4"))
|
||||
|
|
|
|||
|
|
@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
|
|||
|
||||
default:
|
||||
/* Unknown default to latest silicon rev as default*/
|
||||
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
|
||||
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
|
||||
__func__, idcode, hawkeye, rev);
|
||||
omap_revision = DRA752_REV_ES1_1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
|
|||
|
||||
r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
|
||||
if (!IS_ERR(r)) {
|
||||
dev_warn(&od->pdev->dev,
|
||||
dev_dbg(&od->pdev->dev,
|
||||
"alias %s already exists\n", clk_alias);
|
||||
clk_put(r);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
|
|||
oh->mux->pads_dynamic))) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
|
||||
_reconfigure_io_chain();
|
||||
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
_add_initiator_dep(oh, mpu_oh);
|
||||
|
|
@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
|
|||
if (oh->mux && oh->mux->pads_dynamic) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
|
||||
_reconfigure_io_chain();
|
||||
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
oh->_state = _HWMOD_STATE_IDLE;
|
||||
|
|
@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
|
|||
if (!ois)
|
||||
return 0;
|
||||
|
||||
if (ois[0] == NULL) /* Empty list */
|
||||
return 0;
|
||||
|
||||
if (!linkspace) {
|
||||
if (_alloc_linkspace(ois)) {
|
||||
pr_err("omap_hwmod: could not allocate link space\n");
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include "i2c.h"
|
||||
#include "mmc.h"
|
||||
#include "wd_timer.h"
|
||||
#include "soc.h"
|
||||
|
||||
/* Base offset for all DRA7XX interrupts external to MPUSS */
|
||||
#define DRA7XX_IRQ_GIC_START 32
|
||||
|
|
@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|||
&dra7xx_l4_per3__usb_otg_ss1,
|
||||
&dra7xx_l4_per3__usb_otg_ss2,
|
||||
&dra7xx_l4_per3__usb_otg_ss3,
|
||||
&dra7xx_l4_per3__usb_otg_ss4,
|
||||
&dra7xx_l3_main_1__vcp1,
|
||||
&dra7xx_l4_per2__vcp1,
|
||||
&dra7xx_l3_main_1__vcp2,
|
||||
|
|
@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l4_per3__usb_otg_ss4,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init dra7xx_hwmod_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
omap_hwmod_init();
|
||||
return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
||||
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
||||
|
||||
if (!ret && soc_is_dra74x())
|
||||
return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
|
||||
else if (!ret && soc_is_dra72x())
|
||||
return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
|
|||
#define soc_is_omap54xx() 0
|
||||
#define soc_is_omap543x() 0
|
||||
#define soc_is_dra7xx() 0
|
||||
#define soc_is_dra74x() 0
|
||||
#define soc_is_dra72x() 0
|
||||
|
||||
#if defined(MULTI_OMAP2)
|
||||
# if defined(CONFIG_ARCH_OMAP2)
|
||||
|
|
@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
|
||||
#if defined(CONFIG_SOC_DRA7XX)
|
||||
#undef soc_is_dra7xx
|
||||
#undef soc_is_dra74x
|
||||
#undef soc_is_dra72x
|
||||
#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
|
||||
#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
|
||||
#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
|
||||
#endif
|
||||
|
||||
/* Various silicon revisions for omap2 */
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ config ARCH_SH7372
|
|||
select ARM_CPU_SUSPEND if PM || CPU_IDLE
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select SH_INTC
|
||||
select SYS_SUPPORTS_SH_CMT
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
||||
|
|
@ -85,6 +86,7 @@ config ARCH_SH73A0
|
|||
select CPU_V7
|
||||
select I2C
|
||||
select SH_CLK_CPG
|
||||
select SH_INTC
|
||||
select RENESAS_INTC_IRQPIN
|
||||
select SYS_SUPPORTS_SH_CMT
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
|
|
|||
|
|
@ -183,8 +183,8 @@ enum {
|
|||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
/* DIV6 clocks */
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ enum {
|
|||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
/* DIV6 clocks */
|
||||
|
|
|
|||
|
|
@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
|
||||
|
|
|
|||
|
|
@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
|
|||
|
||||
static int ve_init_opp_table(struct device *cpu_dev)
|
||||
{
|
||||
int cluster = topology_physical_package_id(cpu_dev->id);
|
||||
int idx, ret = 0, max_opp = info->num_opps[cluster];
|
||||
struct ve_spc_opp *opps = info->opps[cluster];
|
||||
int cluster;
|
||||
int idx, ret = 0, max_opp;
|
||||
struct ve_spc_opp *opps;
|
||||
|
||||
cluster = topology_physical_package_id(cpu_dev->id);
|
||||
cluster = cluster < 0 ? 0 : cluster;
|
||||
|
||||
max_opp = info->num_opps[cluster];
|
||||
opps = info->opps[cluster];
|
||||
|
||||
for (idx = 0; idx < max_opp; idx++, opps++) {
|
||||
ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
|
||||
|
|
@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
|
|||
spc->hw.init = &init;
|
||||
spc->cluster = topology_physical_package_id(cpu_dev->id);
|
||||
|
||||
spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
|
||||
|
||||
init.name = dev_name(cpu_dev);
|
||||
init.ops = &clk_spc_ops;
|
||||
init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
|
||||
|
|
|
|||
|
|
@ -17,12 +17,6 @@
|
|||
*/
|
||||
.align 5
|
||||
ENTRY(v6_early_abort)
|
||||
#ifdef CONFIG_CPU_V6
|
||||
sub r1, sp, #4 @ Get unused stack location
|
||||
strex r0, r1, [r1] @ Clear the exclusive monitor
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex
|
||||
#endif
|
||||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -13,12 +13,6 @@
|
|||
*/
|
||||
.align 5
|
||||
ENTRY(v7_early_abort)
|
||||
/*
|
||||
* The effect of data aborts on on the exclusive access monitor are
|
||||
* UNPREDICTABLE. Do a CLREX to clear the state
|
||||
*/
|
||||
clrex
|
||||
|
||||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ head-y := arch/arm64/kernel/head.o
|
|||
|
||||
# The byte offset of the kernel image in RAM from the start of RAM.
|
||||
ifeq ($(CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET), y)
|
||||
TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%04x0\n", int(65535 * rand())}')
|
||||
TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%03x000\n", int(512 * rand())}')
|
||||
else
|
||||
TEXT_OFFSET := 0x00080000
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -64,6 +64,8 @@ CONFIG_VIRTIO_BLK=y
|
|||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_ATA=y
|
||||
CONFIG_AHCI_XGENE=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_PATA_PLATFORM=y
|
||||
CONFIG_PATA_OF_PLATFORM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
@ -71,6 +73,7 @@ CONFIG_TUN=y
|
|||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_NET_XGENE=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#define __ASM_SPARSEMEM_H
|
||||
|
||||
#ifdef CONFIG_SPARSEMEM
|
||||
#define MAX_PHYSMEM_BITS 40
|
||||
#define MAX_PHYSMEM_BITS 48
|
||||
#define SECTION_SIZE_BITS 30
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)
|
||||
#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)
|
||||
|
||||
#define __NR_compat_syscalls 383
|
||||
#define __NR_compat_syscalls 386
|
||||
#endif
|
||||
|
||||
#define __ARCH_WANT_SYS_CLONE
|
||||
|
|
|
|||
|
|
@ -787,3 +787,8 @@ __SYSCALL(__NR_sched_setattr, sys_sched_setattr)
|
|||
__SYSCALL(__NR_sched_getattr, sys_sched_getattr)
|
||||
#define __NR_renameat2 382
|
||||
__SYSCALL(__NR_renameat2, sys_renameat2)
|
||||
/* 383 for seccomp */
|
||||
#define __NR_getrandom 384
|
||||
__SYSCALL(__NR_getrandom, sys_getrandom)
|
||||
#define __NR_memfd_create 385
|
||||
__SYSCALL(__NR_memfd_create, sys_memfd_create)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
|
|||
|
||||
if (l1ip != ICACHE_POLICY_PIPT)
|
||||
set_bit(ICACHEF_ALIASING, &__icache_flags);
|
||||
if (l1ip == ICACHE_POLICY_AIVIVT);
|
||||
if (l1ip == ICACHE_POLICY_AIVIVT)
|
||||
set_bit(ICACHEF_AIVIVT, &__icache_flags);
|
||||
|
||||
pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
|
||||
|
|
|
|||
|
|
@ -188,6 +188,8 @@ static __init void reserve_regions(void)
|
|||
if (uefi_debug)
|
||||
pr_cont("\n");
|
||||
}
|
||||
|
||||
set_bit(EFI_MEMMAP, &efi.flags);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -463,6 +465,8 @@ static int __init arm64_enter_virtual_mode(void)
|
|||
efi_native_runtime_setup();
|
||||
set_bit(EFI_RUNTIME_SERVICES, &efi.flags);
|
||||
|
||||
efi.runtime_version = efi.systab->hdr.revision;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unmap:
|
||||
|
|
|
|||
|
|
@ -38,11 +38,11 @@
|
|||
|
||||
#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
|
||||
|
||||
#if (TEXT_OFFSET & 0xf) != 0
|
||||
#error TEXT_OFFSET must be at least 16B aligned
|
||||
#elif (PAGE_OFFSET & 0xfffff) != 0
|
||||
#if (TEXT_OFFSET & 0xfff) != 0
|
||||
#error TEXT_OFFSET must be at least 4KB aligned
|
||||
#elif (PAGE_OFFSET & 0x1fffff) != 0
|
||||
#error PAGE_OFFSET must be at least 2MB aligned
|
||||
#elif TEXT_OFFSET > 0xfffff
|
||||
#elif TEXT_OFFSET > 0x1fffff
|
||||
#error TEXT_OFFSET must be less than 2MB
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1115,19 +1115,15 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
|
|||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
trace_sys_enter(regs, regs->syscallno);
|
||||
|
||||
#ifdef CONFIG_AUDITSYSCALL
|
||||
audit_syscall_entry(syscall_get_arch(), regs->syscallno,
|
||||
regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]);
|
||||
#endif
|
||||
|
||||
return regs->syscallno;
|
||||
}
|
||||
|
||||
asmlinkage void syscall_trace_exit(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_AUDITSYSCALL
|
||||
audit_syscall_exit(regs);
|
||||
#endif
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
trace_sys_exit(regs, regs_return_value(regs));
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/of_fdt.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dma-contiguous.h>
|
||||
#include <linux/efi.h>
|
||||
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/sections.h>
|
||||
|
|
@ -148,7 +149,8 @@ void __init arm64_memblock_init(void)
|
|||
memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start);
|
||||
#endif
|
||||
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
if (!efi_enabled(EFI_MEMMAP))
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
/* 4GB maximum for 32-bit only capable devices */
|
||||
if (IS_ENABLED(CONFIG_ZONE_DMA))
|
||||
|
|
|
|||
|
|
@ -129,7 +129,8 @@ unsigned long get_wchan(struct task_struct *p);
|
|||
#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp)
|
||||
|
||||
#define cpu_relax() barrier()
|
||||
#define cpu_relax() barrier()
|
||||
#define cpu_relax_lowlatency() cpu_relax()
|
||||
|
||||
/* data cache prefetch */
|
||||
#define ARCH_HAS_PREFETCH
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
|
|||
);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -549,8 +549,6 @@ source "drivers/sn/Kconfig"
|
|||
config KEXEC
|
||||
bool "kexec system call"
|
||||
depends on !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
|
||||
|
||||
#define NR_syscalls 316 /* length of syscall table */
|
||||
#define NR_syscalls 317 /* length of syscall table */
|
||||
|
||||
/*
|
||||
* The following defines stop scripts/checksyscalls.sh from complaining about
|
||||
|
|
|
|||
|
|
@ -329,5 +329,6 @@
|
|||
#define __NR_sched_getattr 1337
|
||||
#define __NR_renameat2 1338
|
||||
#define __NR_getrandom 1339
|
||||
#define __NR_memfd_create 1339
|
||||
|
||||
#endif /* _UAPI_ASM_IA64_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -1777,6 +1777,7 @@ sys_call_table:
|
|||
data8 sys_sched_getattr
|
||||
data8 sys_renameat2
|
||||
data8 sys_getrandom
|
||||
data8 sys_memfd_create // 1340
|
||||
|
||||
.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
|
||||
#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
|
||||
|
|
|
|||
|
|
@ -91,8 +91,6 @@ config MMU_SUN3
|
|||
config KEXEC
|
||||
bool "kexec system call"
|
||||
depends on M68KCLASSIC
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -399,5 +399,8 @@
|
|||
#define __NR_sched_setattr 381
|
||||
#define __NR_sched_getattr 382
|
||||
#define __NR_renameat2 383
|
||||
#define __NR_seccomp 384
|
||||
#define __NR_getrandom 385
|
||||
#define __NR_memfd_create 386
|
||||
|
||||
#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -384,3 +384,6 @@ ENTRY(sys_call_table)
|
|||
.long sys_sched_setattr
|
||||
.long sys_sched_getattr
|
||||
.long sys_renameat2
|
||||
.long sys_seccomp
|
||||
.long sys_getrandom /* 385 */
|
||||
.long sys_memfd_create
|
||||
|
|
|
|||
|
|
@ -2396,8 +2396,6 @@ source "kernel/Kconfig.preempt"
|
|||
|
||||
config KEXEC
|
||||
bool "Kexec system call"
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -847,6 +847,7 @@ int __init db1200_dev_setup(void)
|
|||
pr_warn("DB1200: cant get I2C close to 50MHz\n");
|
||||
else
|
||||
clk_set_rate(c, pfc);
|
||||
clk_prepare_enable(c);
|
||||
clk_put(c);
|
||||
}
|
||||
|
||||
|
|
@ -922,11 +923,6 @@ int __init db1200_dev_setup(void)
|
|||
}
|
||||
|
||||
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
|
||||
c = clk_get(NULL, "psc1_intclk");
|
||||
if (!IS_ERR(c)) {
|
||||
clk_prepare_enable(c);
|
||||
clk_put(c);
|
||||
}
|
||||
__raw_writel(PSC_SEL_CLK_SERCLK,
|
||||
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
|
||||
wmb();
|
||||
|
|
|
|||
|
|
@ -59,12 +59,21 @@ static void bcm47xx_machine_restart(char *command)
|
|||
switch (bcm47xx_bus_type) {
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
case BCM47XX_BUS_TYPE_SSB:
|
||||
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
|
||||
if (bcm47xx_bus.ssb.chip_id == 0x4785)
|
||||
write_c0_diag4(1 << 22);
|
||||
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
|
||||
if (bcm47xx_bus.ssb.chip_id == 0x4785) {
|
||||
__asm__ __volatile__(
|
||||
".set\tmips3\n\t"
|
||||
"sync\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
case BCM47XX_BUS_TYPE_BCMA:
|
||||
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
|
||||
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,7 +263,6 @@ static uint64_t crashk_size, crashk_base;
|
|||
static int octeon_uart;
|
||||
|
||||
extern asmlinkage void handle_int(void);
|
||||
extern asmlinkage void plat_irq_dispatch(void);
|
||||
|
||||
/**
|
||||
* Return non zero if we are currently running in the Octeon simulator
|
||||
|
|
@ -458,6 +457,18 @@ static void octeon_halt(void)
|
|||
octeon_kill_core(NULL);
|
||||
}
|
||||
|
||||
static char __read_mostly octeon_system_type[80];
|
||||
|
||||
static int __init init_octeon_system_type(void)
|
||||
{
|
||||
snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
|
||||
cvmx_board_type_to_string(octeon_bootinfo->board_type),
|
||||
octeon_model_get_string(read_c0_prid()));
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_initcall(init_octeon_system_type);
|
||||
|
||||
/**
|
||||
* Return a string representing the system type
|
||||
*
|
||||
|
|
@ -465,11 +476,7 @@ static void octeon_halt(void)
|
|||
*/
|
||||
const char *octeon_board_type_string(void)
|
||||
{
|
||||
static char name[80];
|
||||
sprintf(name, "%s (%s)",
|
||||
cvmx_board_type_to_string(octeon_bootinfo->board_type),
|
||||
octeon_model_get_string(read_c0_prid()));
|
||||
return name;
|
||||
return octeon_system_type;
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2014, Imagination Technologies Ltd.
|
||||
*
|
||||
* EVA functions for generic code
|
||||
*/
|
||||
|
||||
#ifndef _ASM_EVA_H
|
||||
#define _ASM_EVA_H
|
||||
|
||||
#include <kernel-entry-init.h>
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_EVA
|
||||
|
||||
/*
|
||||
* EVA early init code
|
||||
*
|
||||
* Platforms must define their own 'platform_eva_init' macro in
|
||||
* their kernel-entry-init.h header. This macro usually does the
|
||||
* platform specific configuration of the segmentation registers,
|
||||
* and it is normally called from assembly code.
|
||||
*
|
||||
*/
|
||||
|
||||
.macro eva_init
|
||||
platform_eva_init
|
||||
.endm
|
||||
|
||||
#else
|
||||
|
||||
.macro eva_init
|
||||
.endm
|
||||
|
||||
#endif /* CONFIG_EVA */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
#endif
|
||||
#define GICBIS(reg, mask, bits) \
|
||||
do { u32 data; \
|
||||
GICREAD((reg), data); \
|
||||
GICREAD(reg, data); \
|
||||
data &= ~(mask); \
|
||||
data |= ((bits) & (mask)); \
|
||||
GICWRITE((reg), data); \
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ static inline int irq_canonicalize(int irq)
|
|||
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
|
||||
#endif
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void);
|
||||
|
||||
extern void do_IRQ(unsigned int irq);
|
||||
|
||||
extern void arch_init_irq(void);
|
||||
|
|
|
|||
|
|
@ -10,14 +10,15 @@
|
|||
#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* Prepare segments for EVA boot:
|
||||
*
|
||||
* This is in case the processor boots in legacy configuration
|
||||
* (SI_EVAReset is de-asserted and CONFIG5.K == 0)
|
||||
*
|
||||
* On entry, t1 is loaded with CP0_CONFIG
|
||||
*
|
||||
* ========================= Mappings =============================
|
||||
* Virtual memory Physical memory Mapping
|
||||
* 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg)
|
||||
|
|
@ -30,12 +31,20 @@
|
|||
*
|
||||
*
|
||||
* Lowmem is expanded to 2GB
|
||||
*
|
||||
* The following code uses the t0, t1, t2 and ra registers without
|
||||
* previously preserving them.
|
||||
*
|
||||
*/
|
||||
.macro eva_entry
|
||||
.macro platform_eva_init
|
||||
|
||||
.set push
|
||||
.set reorder
|
||||
/*
|
||||
* Get Config.K0 value and use it to program
|
||||
* the segmentation registers
|
||||
*/
|
||||
mfc0 t1, CP0_CONFIG
|
||||
andi t1, 0x7 /* CCA */
|
||||
move t2, t1
|
||||
ins t2, t1, 16, 3
|
||||
|
|
@ -77,6 +86,8 @@
|
|||
mtc0 t0, $16, 5
|
||||
sync
|
||||
jal mips_ihb
|
||||
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro kernel_entry_setup
|
||||
|
|
@ -95,7 +106,7 @@
|
|||
sll t0, t0, 6 /* SC bit */
|
||||
bgez t0, 9f
|
||||
|
||||
eva_entry
|
||||
platform_eva_init
|
||||
b 0f
|
||||
9:
|
||||
/* Assume we came from YAMON... */
|
||||
|
|
@ -127,8 +138,7 @@
|
|||
#ifdef CONFIG_EVA
|
||||
sync
|
||||
ehb
|
||||
mfc0 t1, CP0_CONFIG
|
||||
eva_entry
|
||||
platform_eva_init
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
|
|
|||
|
|
@ -10,13 +10,6 @@
|
|||
|
||||
#include <asm/mach-netlogic/multi-node.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define topology_physical_package_id(cpu) cpu_to_node(cpu)
|
||||
#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
|
||||
#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
|
||||
#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
|
||||
#endif
|
||||
|
||||
#include <asm-generic/topology.h>
|
||||
|
||||
#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
|
||||
|
|
|
|||
|
|
@ -122,6 +122,9 @@ do { \
|
|||
} \
|
||||
} while(0)
|
||||
|
||||
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||
pte_t pteval);
|
||||
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
|
||||
|
|
@ -145,7 +148,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
|
|||
}
|
||||
}
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
|
|
@ -183,7 +185,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
|
|||
}
|
||||
#endif
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
|
|
@ -390,15 +391,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|||
|
||||
extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
|
||||
static inline void update_mmu_cache(struct vm_area_struct *vma,
|
||||
unsigned long address, pte_t *ptep)
|
||||
{
|
||||
pte_t pte = *ptep;
|
||||
__update_tlb(vma, address, pte);
|
||||
__update_cache(vma, address, pte);
|
||||
}
|
||||
|
||||
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
|
||||
|
|
|
|||
|
|
@ -131,10 +131,12 @@ static inline int syscall_get_arch(void)
|
|||
{
|
||||
int arch = EM_MIPS;
|
||||
#ifdef CONFIG_64BIT
|
||||
if (!test_thread_flag(TIF_32BIT_REGS))
|
||||
if (!test_thread_flag(TIF_32BIT_REGS)) {
|
||||
arch |= __AUDIT_ARCH_64BIT;
|
||||
if (test_thread_flag(TIF_32BIT_ADDR))
|
||||
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
|
||||
/* N32 sets only TIF_32BIT_ADDR */
|
||||
if (test_thread_flag(TIF_32BIT_ADDR))
|
||||
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
|
||||
}
|
||||
#endif
|
||||
#if defined(__LITTLE_ENDIAN)
|
||||
arch |= __AUDIT_ARCH_LE;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/eva.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
#include <asm/pm.h>
|
||||
|
|
@ -166,6 +167,9 @@ dcache_done:
|
|||
1: jal mips_cps_core_init
|
||||
nop
|
||||
|
||||
/* Do any EVA initialization if necessary */
|
||||
eva_init
|
||||
|
||||
/*
|
||||
* Boot any other VPEs within this core that should be online, and
|
||||
* deactivate this VPE if it should be offline.
|
||||
|
|
|
|||
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Reference in New Issue