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arm64: dts: uniphier: add reset-names to NAND controller node 

The Denali NAND controller IP has separate reset control for the
controller core and registers.

Add the reset-names, and one more phandle accordingly. This is the
approved DT-binding.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2020-01-16 21:50:45 +09:00
parent e42617b825
commit e98d5023fe
3 changed files with 6 additions and 3 deletions
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3
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View File

@ -633,7 +633,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};

3
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View File

@ -937,7 +937,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};

3
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View File

@ -795,7 +795,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};