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drm/sun4i: dotclock: Fix clock rate read back calcation 

When reading back the divider set in the register, we mask off the
bits that aren't part of the divider. Unfortunately the mask used
here was not converted from the field width.

Fix this by converting the field width to a proper bit mask.

Fixes: 9026e0d122 ("drm: Add Allwinner A10 Display Engine support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2016-09-15 23:14:00 +08:00 committed by Maxime Ripard
parent 9a8aa939ba
commit e996e2089f
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/sun4i/sun4i_dotclock.c
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@ -62,7 +62,7 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
if (!val)
val = 1;