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A few more DT patches for 5.5, mostly: 

- USB3 support for the H6
   - Deinterlacer support for the H3
   - eDP Bridge support on the Teres-I
   - More DT cleanups thanks to the validation
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Merge tag 'sunxi-dt-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

A few more DT patches for 5.5, mostly:
  - USB3 support for the H6
  - Deinterlacer support for the H3
  - eDP Bridge support on the Teres-I
  - More DT cleanups thanks to the validation

* tag 'sunxi-dt-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: h6: Remove useless reset name
  ARM: dts: sun6i: Remove useless reset-names
  arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host support
  arm64: dts: allwinner: h6: add USB3 device nodes
  dt-bindings: Add ANX6345 DP/eDP transmitter binding
  arm64: dts: allwinner: a64: enable ANX6345 bridge on Teres-I
  dts: arm: sun8i: h3: Enable deinterlace unit
  ARM: dts: sunxi: h3/h5: Add MBUS controller node
  dt-bindings: bus: sunxi: Add H3 MBUS compatible

Link: https://lore.kernel.org/r/58ad00a8-9579-4811-969a-a74e331ee9a2.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-06 07:42:02 -08:00
parent f129230b8c 74ab6d9d7d
commit ea21768a8a
8 changed files with 206 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
View File

@ -8,6 +8,7 @@ bus.
Required properties:
- compatible: Must be one of:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
- reg: Offset and length of the register set for the controller
- clocks: phandle to the clock driving the controller
- dma-ranges: See section 2.3.9 of the DeviceTree Specification

102
Documentation/devicetree/bindings/display/bridge/anx6345.yaml Normal file
View File

@ -0,0 +1,102 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analogix ANX6345 eDP Transmitter Device Tree Bindings
maintainers:
- Torsten Duwe <duwe@lst.de>
description: |
The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
portable devices.
properties:
compatible:
const: analogix,anx6345
reg:
maxItems: 1
description: base I2C address of the device
reset-gpios:
maxItems: 1
description: GPIO connected to active low reset
dvdd12-supply:
maxItems: 1
description: Regulator for 1.2V digital core power.
dvdd25-supply:
maxItems: 1
description: Regulator for 2.5V digital core power.
ports:
type: object
properties:
port@0:
type: object
description: |
Video port for LVTTL input
port@1:
type: object
description: |
Video port for eDP output (panel or connector).
May be omitted if EDID works reliably.
required:
- port@0
required:
- compatible
- reg
- reset-gpios
- dvdd12-supply
- dvdd25-supply
- ports
additionalProperties: false
examples:
- |
i2c0 {
#address-cells = <1>;
#size-cells = <0>;
anx6345: anx6345@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>;
dvdd25-supply = <&reg_dldo2>;
dvdd12-supply = <&reg_fldo1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
anx6345_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
anx6345_in_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_anx6345>;
};
};
anx6345_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
anx6345_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
};

1
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -469,7 +469,6 @@ hdmi: hdmi@1c16000 {
<&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>;
reset-names = "ahb";
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
dmas = <&dma 13>, <&dma 13>, <&dma 14>;
status = "disabled";

13
arch/arm/boot/dts/sun8i-h3.dtsi
View File

@ -120,6 +120,19 @@ timer {
};
soc {
deinterlace: deinterlace@1400000 {
compatible = "allwinner,sun8i-h3-deinterlace";
reg = <0x01400000 0x20000>;
clocks = <&ccu CLK_BUS_DEINTERLACE>,
<&ccu CLK_DEINTERLACE>,
<&ccu CLK_DRAM_DEINTERLACE>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_DEINTERLACE>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&mbus 9>;
interconnect-names = "dma-mem";
};
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-h3-system-control";
reg = <0x01c00000 0x1000>;

9
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -109,6 +109,7 @@ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges;
ranges;
display_clocks: clock@1000000 {
@ -543,6 +544,14 @@ external_mdio: mdio@2 {
};
};
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-h3-mbus";
reg = <0x01c62000 0x1000>;
clocks = <&ccu 113>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
#interconnect-cells = <1>;
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;

45
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@ -100,18 +100,41 @@ &dai {
status = "okay";
};
&de {
status = "okay";
};
&ehci1 {
status = "okay";
};
/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
* driver for this chip at the moment, the bootloader initializes it.
* However it can be accessed with the i2c-dev driver from user space.
*/
&i2c0 {
clock-frequency = <100000>;
status = "okay";
anx6345: anx6345@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
dvdd25-supply = <&reg_dldo2>;
dvdd12-supply = <&reg_dldo3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
anx6345_in: endpoint {
remote-endpoint = <&tcon0_out_anx6345>;
};
};
};
};
};
&mixer0 {
status = "okay";
};
&mmc0 {
@ -319,6 +342,20 @@ &sound {
status = "okay";
};
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
status = "okay";
};
&tcon0_out {
tcon0_out_anx6345: endpoint@0 {
reg = <0>;
remote-endpoint = <&anx6345_in>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;

8
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
View File

@ -95,6 +95,10 @@ &de {
status = "okay";
};
&dwc3 {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -310,3 +314,7 @@ &usb2phy {
usb3_vbus-supply = <&reg_vcc5v>;
status = "okay";
};
&usb3phy {
status = "okay";
};

33
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@ -570,6 +570,38 @@ ohci0: usb@5101400 {
status = "disabled";
};
dwc3: dwc3@5200000 {
compatible = "snps,dwc3";
reg = <0x05200000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_XHCI>,
<&ccu CLK_BUS_XHCI>,
<&rtc 0>;
clock-names = "ref", "bus_early", "suspend";
resets = <&ccu RST_BUS_XHCI>;
/*
* The datasheet of the chip doesn't declare the
* peripheral function, and there's no boards known
* to have a USB Type-B port routed to the port.
* In addition, no one has tested the peripheral
* function yet.
* So set the dr_mode to "host" in the DTSI file.
*/
dr_mode = "host";
phys = <&usb3phy>;
phy-names = "usb3-phy";
status = "disabled";
};
usb3phy: phy@5210000 {
compatible = "allwinner,sun50i-h6-usb3-phy";
reg = <0x5210000 0x10000>;
clocks = <&ccu CLK_USB_PHY1>;
resets = <&ccu RST_USB_PHY1>;
#phy-cells = <0>;
status = "disabled";
};
ehci3: usb@5311000 {
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
reg = <0x05311000 0x100>;
@ -649,7 +681,6 @@ tcon_top: tcon-top@6510000 {
"tcon-tv0";
clock-output-names = "tcon-top-tv0";
resets = <&ccu RST_BUS_TCON_TOP>;
reset-names = "rst";
#clock-cells = <1>;
ports {