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ARM: S3C: CPUFREQ: Documentation for cpufreq header
Update arch/arm/plat-s3c/include/plat/cpu-freq.h to include kerneldoc style documentation. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Ben Dooks
Ben Dooks
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2e4ea6e820
commit
ea5fe9aedf
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@ -17,6 +17,21 @@ struct s3c_cpufreq_info;
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struct s3c_cpufreq_board;
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struct s3c_iotimings;
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/**
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* struct s3c_freq - frequency information (mainly for core drivers)
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* @fclk: The FCLK frequency in Hz.
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* @armclk: The ARMCLK frequency in Hz.
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* @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
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* @hclk: The HCLK frequency in Hz.
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* @pclk: The PCLK frequency in Hz.
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*
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* This contains the frequency information about the current configuration
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* mainly for the core drivers to ensure we do not end up passing about
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* a large number of parameters.
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*
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* The @hclk_tns field is a useful cache for the parts of the drivers that
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* need to calculate IO timings and suchlike.
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*/
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struct s3c_freq {
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unsigned long fclk;
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unsigned long armclk;
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@ -25,33 +40,75 @@ struct s3c_freq {
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unsigned long pclk;
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};
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/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
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/**
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* struct s3c_cpufreq_freqs - s3c cpufreq notification information.
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* @freqs: The cpufreq setting information.
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* @old: The old clock settings.
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* @new: The new clock settings.
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* @pll_changing: Set if the PLL is changing.
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*
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* Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
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* notification can use this information that is not provided by just
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* having the core frequency alone.
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*
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* The pll_changing flag is used to indicate if the PLL itself is
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* being set during this change. This is important as the clocks
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* will temporarily be set to the XTAL clock during this time, so
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* drivers may want to close down their output during this time.
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*
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* Note, this is not being used by any current drivers and therefore
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* may be removed in the future.
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*/
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struct s3c_cpufreq_freqs {
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struct cpufreq_freqs freqs;
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struct s3c_freq old;
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struct s3c_freq new;
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unsigned int pll_changing:1;
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};
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#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
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/**
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* struct s3c_clkdivs - clock divisor information
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* @p_divisor: Divisor from FCLK to PCLK.
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* @h_divisor: Divisor from FCLK to HCLK.
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* @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
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* @dvs: Non-zero if using DVS mode for ARMCLK.
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*
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* Divisor settings for the core clocks.
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*/
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struct s3c_clkdivs {
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int p_divisor; /* fclk / pclk */
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int h_divisor; /* fclk / hclk */
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int arm_divisor; /* not all cpus have this. */
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unsigned char dvs; /* using dvs mode to arm. */
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int p_divisor;
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int h_divisor;
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int arm_divisor;
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unsigned char dvs;
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};
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#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
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/**
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* struct s3c_pllval - PLL value entry.
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* @freq: The frequency for this entry in Hz.
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* @pll_reg: The PLL register setting for this PLL value.
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*/
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struct s3c_pllval {
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unsigned long freq;
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unsigned long pll_reg;
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};
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/**
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* struct s3c_cpufreq_config - current cpu frequency configuration
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* @freq: The current settings for the core clocks.
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* @pll: The PLL table entry for the current PLL settings.
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* @divs: The divisor settings for the core clocks.
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* @info: The current core driver information.
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* @board: The information for the board we are running on.
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*
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* This is for the core drivers that need to know information about
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* the current settings and values. It should not be needed by any
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* device drivers.
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*/
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struct s3c_cpufreq_config {
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struct s3c_freq freq;
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struct s3c_pllval pll;
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@ -60,13 +117,27 @@ struct s3c_cpufreq_config {
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struct s3c_cpufreq_board *board;
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};
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/* s3c_cpufreq_board
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/**
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* struct s3c_cpufreq_board - per-board cpu frequency informatin
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* @refresh: The SDRAM refresh period in nanoseconds.
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* @auto_io: Set if the IO timing settings should be generated from the
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* initialisation time hardware registers.
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* @need_io: Set if the board has external IO on any of the chipselect
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* lines that will require the hardware timing registers to be
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* updated on a clock change.
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* @max: The maxium frequency limits for the system. Any field that
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* is left at zero will use the CPU's settings.
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*
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* per-board configuraton information, such as memory refresh and
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* how to initialise IO timings.
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* This contains the board specific settings that affect how the CPU
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* drivers chose settings. These include the memory refresh and IO
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* timing information.
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*
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* Registration depends on the driver being used, the ARMCLK only
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* implementation does not currently need this but the older style
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* driver requires this to be available.
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*/
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struct s3c_cpufreq_board {
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unsigned int refresh; /* refresh period in ns */
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unsigned int refresh;
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unsigned int auto_io:1; /* automatically init io timings. */
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unsigned int need_io:1; /* set if needs io timing support. */
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