powerpc/fsl: Update fman dt binding with pcs-phy and tbi-phy

The FMan contains internal PHY devices used for SGMII connections
to external PHYs. When these PHYs are in use a reference is needed
for both the external PHY and the internal one. For the external
PHY phy-handle provides the reference. For the internal PHY a new
handle is required.
In dTSEC, the internal PHY is a TBI (Ten Bit Interface) PHY,
the handle used will be tbi-handle.
In mEMAC, the internal PHY is a PCS (Physical Coding Sublayer) PHY,
the handle used will be pcsphy-handle.

Signed-off-by: Igal Liberman <igal.liberman@freescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
Igal Liberman 2015-12-24 03:42:11 +02:00 committed by Scott Wood
parent 6becef7ea0
commit ea6370d23c
1 changed files with 40 additions and 0 deletions

View File

@ -315,6 +315,16 @@ PROPERTIES
Value type: <phandle> Value type: <phandle>
Definition: A phandle for 1EEE1588 timer. Definition: A phandle for 1EEE1588 timer.
- pcsphy-handle
Usage required for "fsl,fman-memac" MACs
Value type: <phandle>
Definition: A phandle for pcsphy.
- tbi-handle
Usage required for "fsl,fman-dtsec" MACs
Value type: <phandle>
Definition: A phandle for tbiphy.
EXAMPLE EXAMPLE
fman1_tx28: port@a8000 { fman1_tx28: port@a8000 {
@ -340,6 +350,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
ptp-timer = <&ptp-timer>; ptp-timer = <&ptp-timer>;
tbi-handle = <&tbi0>;
}; };
============================================================================ ============================================================================
@ -415,6 +426,13 @@ PROPERTIES
The settings and programming routines for internal/external The settings and programming routines for internal/external
MDIO are different. Must be included for internal MDIO. MDIO are different. Must be included for internal MDIO.
For internal PHY device on internal mdio bus, a PHY node should be created.
See the definition of the PHY node in booting-without-of.txt for an
example of how to define a PHY (Internal PHY has no interrupt line).
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
PCS PHY addr must be '0'.
EXAMPLE EXAMPLE
Example for FMan v2 external MDIO: Example for FMan v2 external MDIO:
@ -425,12 +443,29 @@ mdio@f1000 {
interrupts = <101 2 0 0>; interrupts = <101 2 0 0>;
}; };
Example for FMan v2 internal MDIO:
mdio@e3120 {
compatible = "fsl,fman-mdio";
reg = <0xe3120 0xee0>;
fsl,fman-internal-mdio;
tbi1: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
Example for FMan v3 internal MDIO: Example for FMan v3 internal MDIO:
mdio@f1000 { mdio@f1000 {
compatible = "fsl,fman-memac-mdio"; compatible = "fsl,fman-memac-mdio";
reg = <0xf1000 0x1000>; reg = <0xf1000 0x1000>;
fsl,fman-internal-mdio; fsl,fman-internal-mdio;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
}; };
============================================================================= =============================================================================
@ -568,6 +603,7 @@ fman@400000 {
cell-index = <0>; cell-index = <0>;
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
tbi-handle = <&tbi5>;
}; };
ethernet@e2000 { ethernet@e2000 {
@ -575,6 +611,7 @@ fman@400000 {
cell-index = <1>; cell-index = <1>;
reg = <0xe2000 0x1000>; reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
tbi-handle = <&tbi6>;
}; };
ethernet@e4000 { ethernet@e4000 {
@ -582,6 +619,7 @@ fman@400000 {
cell-index = <2>; cell-index = <2>;
reg = <0xe4000 0x1000>; reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
tbi-handle = <&tbi7>;
}; };
ethernet@e6000 { ethernet@e6000 {
@ -589,6 +627,7 @@ fman@400000 {
cell-index = <3>; cell-index = <3>;
reg = <0xe6000 0x1000>; reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
tbi-handle = <&tbi8>;
}; };
ethernet@e8000 { ethernet@e8000 {
@ -596,6 +635,7 @@ fman@400000 {
cell-index = <4>; cell-index = <4>;
reg = <0xf0000 0x1000>; reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
tbi-handle = <&tbi9>;
ethernet@f0000 { ethernet@f0000 {
cell-index = <8>; cell-index = <8>;