mirror of https://gitee.com/openkylin/linux.git
tile PCI RC: bomb comments and whitespace format
This change is purely stylistic but improves the readability of the tile PCI RC driver. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
f62f73f6ca
commit
eafa5c8a10
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@ -108,17 +108,15 @@ static struct pci_ops tile_cfg_ops;
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/* Mask of CPUs that should receive PCIe interrupts. */
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static struct cpumask intr_cpus_map;
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/*
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* We don't need to worry about the alignment of resources.
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*/
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/* We don't need to worry about the alignment of resources. */
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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resource_size_t size,
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resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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* Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
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* For now, we simply send interrupts to non-dataplane CPUs.
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@ -146,25 +144,19 @@ static int tile_irq_cpu(int irq)
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return cpu;
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}
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/*
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* Open a file descriptor to the TRIO shim.
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*/
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/* Open a file descriptor to the TRIO shim. */
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static int tile_pcie_open(int trio_index)
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{
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gxio_trio_context_t *context = &trio_contexts[trio_index];
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int ret;
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int mac;
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/*
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* This opens a file descriptor to the TRIO shim.
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*/
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/* This opens a file descriptor to the TRIO shim. */
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ret = gxio_trio_init(context, trio_index);
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if (ret < 0)
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goto gxio_trio_init_failure;
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/*
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* Allocate an ASID for the kernel.
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*/
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/* Allocate an ASID for the kernel. */
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ret = gxio_trio_alloc_asids(context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
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@ -285,20 +277,17 @@ static int __init tile_trio_init(void)
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}
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postcore_initcall(tile_trio_init);
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static void
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tilegx_legacy_irq_ack(struct irq_data *d)
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static void tilegx_legacy_irq_ack(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
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}
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static void
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tilegx_legacy_irq_mask(struct irq_data *d)
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static void tilegx_legacy_irq_mask(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
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}
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static void
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tilegx_legacy_irq_unmask(struct irq_data *d)
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static void tilegx_legacy_irq_unmask(struct irq_data *d)
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{
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__insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
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}
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@ -319,8 +308,7 @@ static struct irq_chip tilegx_legacy_irq_chip = {
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* to Linux which just calls handle_level_irq() after clearing the
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* MAC INTx Assert status bit associated with this interrupt.
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*/
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static void
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trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
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static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct pci_controller *controller = irq_desc_get_handler_data(desc);
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gxio_trio_context_t *trio_context = controller->trio;
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@ -386,9 +374,7 @@ static int tile_init_irqs(struct pci_controller *controller)
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goto free_irqs;
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}
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/*
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* Register the IRQ handler with the kernel.
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*/
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/* Register the IRQ handler with the kernel. */
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irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
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trio_handle_level_irq);
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irq_set_chip_data(irq, (void *)(uint64_t)i);
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@ -471,15 +457,11 @@ int __init tile_pci_init(void)
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}
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}
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/*
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* Return if no PCIe ports are configured to operate in RC mode.
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*/
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/* Return if no PCIe ports are configured to operate in RC mode. */
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if (num_rc_controllers == 0)
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return 0;
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/*
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* Set the TRIO pointer and MAC index for each PCIe RC port.
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*/
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/* Set the TRIO pointer and MAC index for each PCIe RC port. */
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for (i = 0; i < TILEGX_NUM_TRIO; i++) {
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for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
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if (pcie_rc[i][j]) {
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@ -495,14 +477,10 @@ int __init tile_pci_init(void)
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}
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out:
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/*
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* Configure each PCIe RC port.
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*/
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/* Configure each PCIe RC port. */
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for (i = 0; i < num_rc_controllers; i++) {
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/*
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* Configure the PCIe MAC to run in RC mode.
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*/
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/* Configure the PCIe MAC to run in RC mode. */
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struct pci_controller *controller = &pci_controllers[i];
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controller->index = i;
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@ -525,7 +503,6 @@ int __init tile_pci_init(void)
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* is in range [3GB, 4GB - 1] of a 4GB space beyond the
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* PA space.
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*/
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controller->mem_offset = TILE_PCI_MEM_START +
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(i * TILE_PCI_BAR_WINDOW_TOP);
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controller->mem_space.start = controller->mem_offset +
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@ -553,7 +530,6 @@ static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
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return controller->irq_intx_table[pin - 1];
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}
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static void fixup_read_and_payload_sizes(struct pci_controller *controller)
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{
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gxio_trio_context_t *trio_context = controller->trio;
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@ -567,9 +543,7 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller)
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mac = controller->mac;
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/*
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* Set our max read request size to be 4KB.
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*/
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/* Set our max read request size to be 4KB. */
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reg_offset =
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(TRIO_PCIE_RC_DEVICE_CONTROL <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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@ -578,10 +552,10 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller)
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(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
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dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
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reg_offset);
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reg_offset);
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dev_control.max_read_req_sz = 5;
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__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
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dev_control.word);
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dev_control.word);
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/*
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* Set the max payload size supported by this Gx PCIe MAC.
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@ -597,10 +571,10 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller)
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(mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
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rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
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reg_offset);
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reg_offset);
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rc_dev_cap.mps_sup = 1;
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__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
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rc_dev_cap.word);
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rc_dev_cap.word);
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/* Configure PCI Express MPS setting. */
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list_for_each_entry(child, &root_bus->children, node) {
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@ -628,7 +602,7 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller)
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dev_control.max_payload_size,
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dev_control.max_read_req_sz,
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mac);
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if (err < 0) {
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if (err < 0) {
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pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
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"MAC %d on TRIO %d\n",
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mac, controller->trio_index);
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@ -672,9 +646,7 @@ static int setup_pcie_rc_delay(char *str)
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}
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early_param("pcie_rc_delay", setup_pcie_rc_delay);
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/*
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* PCI initialization entry point, called by subsys_initcall.
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*/
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/* PCI initialization entry point, called by subsys_initcall. */
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int __init pcibios_init(void)
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{
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resource_size_t offset;
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@ -744,9 +716,7 @@ int __init pcibios_init(void)
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pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
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trio_index, controller->mac);
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/*
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* Delay the bus probe if needed.
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*/
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/* Delay the bus probe if needed. */
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if (rc_delay[trio_index][mac]) {
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pr_info("Delaying PCIe RC bus enumerating %d sec"
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" on MAC %d on TRIO %d\n",
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@ -761,9 +731,7 @@ int __init pcibios_init(void)
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msleep(1000);
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}
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/*
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* Check for PCIe link-up status again.
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*/
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/* Check for PCIe link-up status again. */
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port_status.word =
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__gxio_mmio_read(trio_context->mmio_base_mac +
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reg_offset);
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@ -801,7 +769,6 @@ int __init pcibios_init(void)
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* Change the device ID so that Linux bus crawl doesn't confuse
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* the internal bridge with any Tilera endpoints.
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*/
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reg_offset =
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(TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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@ -814,10 +781,7 @@ int __init pcibios_init(void)
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TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
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TILERA_VENDOR_ID);
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/*
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* Set the internal P2P bridge class code.
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*/
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/* Set the internal P2P bridge class code. */
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reg_offset =
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(TRIO_PCIE_RC_REVISION_ID <<
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TRIO_CFG_REGION_ADDR__REG_SHIFT) |
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@ -828,26 +792,22 @@ int __init pcibios_init(void)
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class_code_revision =
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__gxio_mmio_read32(trio_context->mmio_base_mac +
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reg_offset);
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class_code_revision = (class_code_revision & 0xff ) |
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(PCI_CLASS_BRIDGE_PCI << 16);
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class_code_revision = (class_code_revision & 0xff) |
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(PCI_CLASS_BRIDGE_PCI << 16);
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__gxio_mmio_write32(trio_context->mmio_base_mac +
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reg_offset, class_code_revision);
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#ifdef USE_SHARED_PCIE_CONFIG_REGION
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/*
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* Map in the MMIO space for the PIO region.
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*/
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/* Map in the MMIO space for the PIO region. */
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offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
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(((unsigned long long)mac) <<
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TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
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#else
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/*
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* Alloc a PIO region for PCI config access per MAC.
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*/
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/* Alloc a PIO region for PCI config access per MAC. */
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ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
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@ -858,9 +818,7 @@ int __init pcibios_init(void)
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trio_context->pio_cfg_index[mac] = ret;
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/*
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* For PIO CFG, the bus_address_hi parameter is 0.
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*/
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/* For PIO CFG, the bus_address_hi parameter is 0. */
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ret = gxio_trio_init_pio_region_aux(trio_context,
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trio_context->pio_cfg_index[mac],
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mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
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@ -887,9 +845,7 @@ int __init pcibios_init(void)
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continue;
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}
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/*
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* Initialize the PCIe interrupts.
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*/
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/* Initialize the PCIe interrupts. */
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if (tile_init_irqs(controller)) {
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pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
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mac, trio_index);
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@ -921,7 +877,6 @@ int __init pcibios_init(void)
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* It allocates all of the resources (I/O memory, etc)
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* associated with the devices read in above.
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*/
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pci_assign_unassigned_resources();
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/* Record the I/O resources in the PCI controller structure. */
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@ -942,14 +897,12 @@ int __init pcibios_init(void)
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/* Configure the max_payload_size values for this domain. */
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fixup_read_and_payload_sizes(controller);
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/*
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* Alloc a PIO region for PCI memory access for each RC port.
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*/
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/* Alloc a PIO region for PCI memory access for each RC port. */
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ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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@ -967,8 +920,8 @@ int __init pcibios_init(void)
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0);
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if (ret < 0) {
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pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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@ -980,8 +933,8 @@ int __init pcibios_init(void)
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ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
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if (ret < 0) {
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pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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@ -999,8 +952,8 @@ int __init pcibios_init(void)
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HV_TRIO_PIO_FLAG_IO_SPACE);
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if (ret < 0) {
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pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, "
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"give up\n", controller->trio_index,
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controller->mac);
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"give up\n", controller->trio_index,
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controller->mac);
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continue;
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}
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@ -1020,9 +973,9 @@ int __init pcibios_init(void)
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0);
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if (ret < 0) {
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pr_err("PCI: Mem-Map alloc failure on TRIO %d "
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"mac %d for MC %d, give up\n",
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controller->trio_index,
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controller->mac, j);
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"mac %d for MC %d, give up\n",
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controller->trio_index,
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controller->mac, j);
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goto alloc_mem_map_failed;
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}
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@ -1053,9 +1006,9 @@ int __init pcibios_init(void)
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GXIO_TRIO_ORDER_MODE_UNORDERED);
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if (ret < 0) {
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pr_err("PCI: Mem-Map init failure on TRIO %d "
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"mac %d for MC %d, give up\n",
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controller->trio_index,
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controller->mac, j);
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"mac %d for MC %d, give up\n",
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controller->trio_index,
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controller->mac, j);
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goto alloc_mem_map_failed;
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}
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@ -1064,22 +1017,18 @@ int __init pcibios_init(void)
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alloc_mem_map_failed:
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break;
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}
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}
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return 0;
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}
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subsys_initcall(pcibios_init);
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/* Note: to be deleted after Linux 3.6 merge. */
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/* No bus fixups needed. */
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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}
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/*
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* This can be called from the generic PCI layer, but doesn't need to
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* do anything.
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*/
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/* Process any "pci=" kernel boot arguments. */
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char *pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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@ -1130,7 +1079,6 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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* By searching phys_addr in each controller's mem_space, we can
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* determine the controller that should accept the PCI memory access.
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*/
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for (i = 0; i < num_rc_controllers; i++) {
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/*
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* Skip controllers that are not properly initialized or
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@ -1158,9 +1106,7 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
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/*
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* We need to keep the PCI bus address's in-page offset in the VA.
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*/
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/* We need to keep the PCI bus address's in-page offset in the VA. */
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return iorpc_ioremap(trio_fd, offset, size) +
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(start & (PAGE_SIZE - 1));
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}
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|
|
@ -1186,7 +1132,6 @@ void __iomem *ioport_map(unsigned long port, unsigned int size)
|
|||
* By searching the port in each controller's io_space, we can
|
||||
* determine the controller that should accept the PCI I/O access.
|
||||
*/
|
||||
|
||||
for (i = 0; i < num_rc_controllers; i++) {
|
||||
/*
|
||||
* Skip controllers that are not properly initialized or
|
||||
|
|
@ -1214,9 +1159,7 @@ void __iomem *ioport_map(unsigned long port, unsigned int size)
|
|||
|
||||
offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
|
||||
|
||||
/*
|
||||
* We need to keep the PCI bus address's in-page offset in the VA.
|
||||
*/
|
||||
/* We need to keep the PCI bus address's in-page offset in the VA. */
|
||||
return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_map);
|
||||
|
|
@ -1249,7 +1192,6 @@ EXPORT_SYMBOL(pci_iounmap);
|
|||
* offset is in bytes, from the start of config space for the
|
||||
* specified bus & device.
|
||||
*/
|
||||
|
||||
static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
|
||||
int size, u32 *val)
|
||||
{
|
||||
|
|
@ -1299,7 +1241,6 @@ static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
|
|||
* Accesses to the directly attached device have to be
|
||||
* sent as type-0 configs.
|
||||
*/
|
||||
|
||||
if (busnum == (controller->first_busno + 1)) {
|
||||
/*
|
||||
* There is only one device off of our built-in P2P bridge.
|
||||
|
|
@ -1321,9 +1262,8 @@ static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
|
|||
* Note that we don't set the mac field in cfg_addr because the
|
||||
* mapping is per port.
|
||||
*/
|
||||
|
||||
mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
|
||||
cfg_addr.word;
|
||||
cfg_addr.word;
|
||||
|
||||
valid_device:
|
||||
|
||||
|
|
@ -1427,7 +1367,6 @@ static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
|
|||
* Accesses to the directly attached device have to be
|
||||
* sent as type-0 configs.
|
||||
*/
|
||||
|
||||
if (busnum == (controller->first_busno + 1)) {
|
||||
/*
|
||||
* There is only one device off of our built-in P2P bridge.
|
||||
|
|
@ -1449,7 +1388,6 @@ static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
|
|||
* Note that we don't set the mac field in cfg_addr because the
|
||||
* mapping is per port.
|
||||
*/
|
||||
|
||||
mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
|
||||
cfg_addr.word;
|
||||
|
||||
|
|
@ -1487,11 +1425,8 @@ static struct pci_ops tile_cfg_ops = {
|
|||
};
|
||||
|
||||
|
||||
/*
|
||||
* MSI support starts here.
|
||||
*/
|
||||
static unsigned int
|
||||
tilegx_msi_startup(struct irq_data *d)
|
||||
/* MSI support starts here. */
|
||||
static unsigned int tilegx_msi_startup(struct irq_data *d)
|
||||
{
|
||||
if (d->msi_desc)
|
||||
unmask_msi_irq(d);
|
||||
|
|
@ -1499,21 +1434,18 @@ tilegx_msi_startup(struct irq_data *d)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
tilegx_msi_ack(struct irq_data *d)
|
||||
static void tilegx_msi_ack(struct irq_data *d)
|
||||
{
|
||||
__insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
|
||||
}
|
||||
|
||||
static void
|
||||
tilegx_msi_mask(struct irq_data *d)
|
||||
static void tilegx_msi_mask(struct irq_data *d)
|
||||
{
|
||||
mask_msi_irq(d);
|
||||
__insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
|
||||
}
|
||||
|
||||
static void
|
||||
tilegx_msi_unmask(struct irq_data *d)
|
||||
static void tilegx_msi_unmask(struct irq_data *d)
|
||||
{
|
||||
__insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
|
||||
unmask_msi_irq(d);
|
||||
|
|
|
|||
Loading…
Reference in New Issue