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staging: mt7621-eth: Document ralink/mediatek SoC ethernet binding
Add possible dt binding for mediatek gigabit switches. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Michael Lee <igvtee@gmail.com> Cc: devicetree@vger.kernel.org Signed-off-by: NeilBrown <neil@brown.name> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Mediatek Gigabit Switch
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=======================
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The mediatek gigabit switch can be found on Mediatek SoCs.
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Required properties:
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- compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw",
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"mediatek,mt7623-gsw"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the gigabit switches interrupt
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Additional required properties for ARM based SoCs:
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- mediatek,reset-pin: phandle describing the reset GPIO
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- clocks: the clocks used by the switch
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- clock-names: the names of the clocks listed in the clocks property
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these should be "trgpll", "esw", "gp2", "gp1"
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- mt7530-supply: the phandle of the regulator used to power the switch
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- mediatek,pctl-regmap: phandle to the port control regmap. this is used to
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setup the drive current
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Optional properties:
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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Example:
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gsw: switch@1b100000 {
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compatible = "mediatek,mt7623-gsw";
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reg = <0 0x1b110000 0 0x300000>;
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interrupt-parent = <&pio>;
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interrupts = <168 IRQ_TYPE_EDGE_RISING>;
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clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
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<ðsys CLK_ETHSYS_ESW>,
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<ðsys CLK_ETHSYS_GP2>,
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<ðsys CLK_ETHSYS_GP1>;
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clock-names = "trgpll", "esw", "gp2", "gp1";
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mt7530-supply = <&mt6323_vpa_reg>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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mediatek,reset-pin = <&pio 15 0>;
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status = "okay";
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};
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- verify devicetree documentation is consistent with code
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Cc: NeilBrown <neil@brown.name>
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