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ASoC: es8316: support fixed and variable both clock rates 

This patch supports some type of machine drivers that set 0 to mclk
when sound device goes to idle state. After applied this patch,
sysclk == 0 means there is no constraint of sound rate and other
values will set constraints which is derived by sysclk setting.

Original code refuses sysclk == 0 setting. But some boards and SoC
(such as RockPro64 and RockChip I2S) has connected SoC MCLK out to
ES8316 MCLK in. In this case, SoC side I2S will choose suitable
frequency of MCLK such as fs * mclk-fs when user starts playing or
capturing.

Bad scenario as follows (mclk-fs = 256):
  - Initialize sysclk by correct value (Ex. 12.288MHz)
    - ES8316 set constraints of PCM rate by sysclk
      48kHz (1/256), 32kHz (1/384), 30.720kHz (1/400),
      24kHz (1/512), 16kHz (1/768), 12kHz (1/1024)
  - Play 48kHz sound, it's acceptable
  - Sysclk is not changed

  - Play 32kHz sound, it's acceptable
  - Set sysclk by 8.192MHz (= fs * mclk-fs = 32k * 256)
    - ES8316 set constraints of PCM rate by sysclk
      32kHz (1/256), 21.33kHz (1/384), 20.48kHz (1/400),
      16kHz (1/512), 10.66kHz (1/768), 8kHz (1/1024)

  - Play 48kHz again, but it's NOT acceptable because constraints
    list does not allow 48kHz

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Link: https://lore.kernel.org/r/20190907163653.9382-2-katsuhiro@katsuster.net
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Katsuhiro Suzuki 2019-09-08 01:36:53 +09:00 committed by Mark Brown
parent 0db0c62c88
commit ebe02a5b9e
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 20 additions and 15 deletions
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35
sound/soc/codecs/es8316.c
View File

@ -367,8 +367,12 @@ static int es8316_set_dai_sysclk(struct snd_soc_dai *codec_dai,
es8316->sysclk = freq; es8316->sysclk = freq;
if (freq == 0) if (freq == 0) {
es8316->sysclk_constraints.list = NULL;
es8316->sysclk_constraints.count = 0;
return 0; return 0;
}
ret = clk_set_rate(es8316->mclk, freq); ret = clk_set_rate(es8316->mclk, freq);
if (ret) if (ret)
@ -447,17 +451,10 @@ static int es8316_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_component *component = dai->component; struct snd_soc_component *component = dai->component;
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component); struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
if (es8316->sysclk == 0) { if (es8316->sysclk_constraints.list)
dev_err(component->dev, "No sysclk provided\n"); snd_pcm_hw_constraint_list(substream->runtime, 0,
return -EINVAL; SNDRV_PCM_HW_PARAM_RATE,
} &es8316->sysclk_constraints);
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC.
*/
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&es8316->sysclk_constraints);
return 0; return 0;
} }
@ -469,11 +466,19 @@ static int es8316_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_component *component = dai->component; struct snd_soc_component *component = dai->component;
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component); struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
u8 wordlen = 0; u8 wordlen = 0;
int i;
if (!es8316->sysclk) { /* Validate supported sample rates that are autodetected from MCLK */
dev_err(component->dev, "No MCLK configured\n"); for (i = 0; i < NR_SUPPORTED_MCLK_LRCK_RATIOS; i++) {
return -EINVAL; const unsigned int ratio = supported_mclk_lrck_ratios[i];
if (es8316->sysclk % ratio != 0)
continue;
if (es8316->sysclk / ratio == params_rate(params))
break;
} }
if (i == NR_SUPPORTED_MCLK_LRCK_RATIOS)
return -EINVAL;
switch (params_format(params)) { switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_LE: