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mlxsw: reg: Update module_type values in PMTM register and map them to width 

There are couple new values that PMTM register can return
in module_type field. Add them and map them to module width in
mlxsw_core_module_max_width(). Fix the existing names on the way.

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko 2020-02-27 20:59:26 +01:00 committed by David S. Miller
parent 37e1244a79
commit ec4a514a68
2 changed files with 31 additions and 8 deletions
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17
drivers/net/ethernet/mellanox/mlxsw/core.c
View File

@ -2201,13 +2201,22 @@ int mlxsw_core_module_max_width(struct mlxsw_core *mlxsw_core, u8 module)
/* Here we need to get the module width according to the module type. */
switch (module_type) {
case MLXSW_REG_PMTM_MODULE_TYPE_C2C8X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_OSFP:
return 8;
case MLXSW_REG_PMTM_MODULE_TYPE_C2C4X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_BP_4X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP:
case MLXSW_REG_PMTM_MODULE_TYPE_QSFP:
return 4;
case MLXSW_REG_PMTM_MODULE_TYPE_BP_2X:
case MLXSW_REG_PMTM_MODULE_TYPE_C2C2X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_BP_2X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_DSFP:
return 2;
case MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_BP_1X:
case MLXSW_REG_PMTM_MODULE_TYPE_C2C1X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_BP_1X: /* fall through */
case MLXSW_REG_PMTM_MODULE_TYPE_SFP:
return 1;
default:
return -EINVAL;

22
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@ -5440,15 +5440,29 @@ enum mlxsw_reg_pmtm_module_type {
/* Backplane with 4 lanes */
MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
/* QSFP */
MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP,
MLXSW_REG_PMTM_MODULE_TYPE_QSFP,
/* SFP */
MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP,
MLXSW_REG_PMTM_MODULE_TYPE_SFP,
/* Backplane with single lane */
MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
/* Backplane with two lane */
MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
/* Chip2Chip */
MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10,
/* Chip2Chip4x */
MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10,
/* Chip2Chip2x */
MLXSW_REG_PMTM_MODULE_TYPE_C2C2X,
/* Chip2Chip1x */
MLXSW_REG_PMTM_MODULE_TYPE_C2C1X,
/* QSFP-DD */
MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
/* OSFP */
MLXSW_REG_PMTM_MODULE_TYPE_OSFP,
/* SFP-DD */
MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD,
/* DSFP */
MLXSW_REG_PMTM_MODULE_TYPE_DSFP,
/* Chip2Chip8x */
MLXSW_REG_PMTM_MODULE_TYPE_C2C8X,
};
/* reg_pmtm_module_type