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Merge branch 'pci/host-mvebu' into next
* pci/host-mvebu: PCI: mvebu: Call request_resource() on the apertures bus: mvebu-mbus: Fix incorrect size for PCI aperture resources PCI: mvebu: Fix potential issue in range parsing PCI: mvebu: Use Device ID and revision from underlying endpoint
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commit
ec5130ba79
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@ -870,14 +870,14 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
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ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
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if (!ret) {
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mem->start = reg[0];
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mem->end = mem->start + reg[1];
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mem->end = mem->start + reg[1] - 1;
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mem->flags = IORESOURCE_MEM;
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}
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ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
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if (!ret) {
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io->start = reg[0];
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io->end = io->start + reg[1];
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io->end = io->start + reg[1] - 1;
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io->flags = IORESOURCE_IO;
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}
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}
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@ -60,14 +60,6 @@
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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/*
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* This product ID is registered by Marvell, and used when the Marvell
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* SoC is not the root complex, but an endpoint on the PCIe bus. It is
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* therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
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* bridge.
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*/
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#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
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/* PCI configuration space of a PCI-to-PCI bridge */
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struct mvebu_sw_pci_bridge {
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u16 vendor;
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@ -109,7 +101,9 @@ struct mvebu_pcie {
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struct mvebu_pcie_port *ports;
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struct msi_chip *msi;
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struct resource io;
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char io_name[30];
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struct resource realio;
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char mem_name[30];
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struct resource mem;
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struct resource busn;
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int nports;
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@ -388,7 +382,8 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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bridge->class = PCI_CLASS_BRIDGE_PCI;
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bridge->vendor = PCI_VENDOR_ID_MARVELL;
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bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
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bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
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bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
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bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->cache_line_size = 0x10;
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@ -679,10 +674,30 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(sys);
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int i;
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int domain = 0;
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if (resource_size(&pcie->realio) != 0)
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#ifdef CONFIG_PCI_DOMAINS
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domain = sys->domain;
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#endif
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snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
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domain);
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pcie->mem.name = pcie->mem_name;
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snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
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pcie->realio.name = pcie->io_name;
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if (request_resource(&iomem_resource, &pcie->mem))
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return 0;
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if (resource_size(&pcie->realio) != 0) {
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if (request_resource(&ioport_resource, &pcie->realio)) {
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release_resource(&pcie->mem);
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return 0;
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}
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pci_add_resource_offset(&sys->resources, &pcie->realio,
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sys->io_offset);
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}
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pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
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pci_add_resource(&sys->resources, &pcie->busn);
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@ -804,7 +819,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
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for (i = 0; i < nranges; i++) {
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u32 flags = of_read_number(range, 1);
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u32 slot = of_read_number(range, 2);
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u32 slot = of_read_number(range + 1, 1);
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u64 cpuaddr = of_read_number(range + na, pna);
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unsigned long rtype;
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