mirror of https://gitee.com/openkylin/linux.git
ARM: sunxi: add PLL4 support
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -66,6 +66,13 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@ -63,6 +63,13 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@ -67,6 +67,13 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@ -62,6 +62,13 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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